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Mixed-Signal Design

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  • Discussion

    [SOLVED] unable to compile with genvar variable in veriloga

    Category: Mixed-Signal Design

    By msharma

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    updated over 10 years ago by msharma

    2 replies • 21151 views
  • Discussion

    SystemVerilog import into DFII

    Category: Mixed-Signal Design

    By Cotomaznamenat

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    updated over 10 years ago by Cotomaznamenat

    2 replies • 16438 views
  • Discussion

    Import a non-linear electro-thermal reduced-order model in SPECTRE ?

    Category: Mixed-Signal Design

    By Herge

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    started over 10 years ago

    0 replies • 13448 views
  • Discussion

    Regarding Cadence Virtuoso gpdk45nm technology spectre model file.

    Category: Mixed-Signal Design

    By PS90

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    started over 10 years ago

    0 replies • 13606 views
  • Discussion

    Spectre received SIGTERM

    Category: Mixed-Signal Design

    By PirateKing2008

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    updated over 10 years ago by Andrew Beckett

    1 replies • 16363 views
  • Discussion

    Verilog HDL simulation with ams simulator

    Category: Mixed-Signal Design

    By Medya

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    updated over 10 years ago by Andrew Beckett

    1 replies • 15276 views
  • Discussion

    need help with SV resolution function

    Category: Mixed-Signal Design

    By golanp

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    started over 10 years ago

    0 replies • 13740 views
  • Discussion

    Currents in VerilogAMS model "do not evaluate to an object that can be plotted"

    Category: Mixed-Signal Design

    By mazorra

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    updated over 10 years ago by Andrew Beckett

    3 replies • 2526 views
  • Discussion

    specifying libraries to exclude during compilation

    Category: Mixed-Signal Design

    By HPetrow

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    updated over 10 years ago by HPetrow

    2 replies • 14478 views
  • Discussion

    how can I use netlist ??

    Category: Mixed-Signal Design

    By mohamedly

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    updated over 10 years ago by mohamedly

    4 replies • 14535 views
  • Discussion

    spice netlist in cadence

    Category: Mixed-Signal Design

    By mohamedly

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    updated over 10 years ago by Andrew Beckett

    1 replies • 15176 views
  • Discussion

    AMS Verilog module parameter passing

    Category: Mixed-Signal Design

    By Cogito

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    updated over 10 years ago by Andrew Beckett

    1 replies • 15840 views
  • Discussion

    How to give initial condition in a test bench

    Category: Mixed-Signal Design

    By Apoorv1

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    updated over 10 years ago by Andrew Beckett

    1 replies • 15847 views
  • Discussion

    Simulation Directory

    Category: Mixed-Signal Design

    By analogy

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    •

    updated over 10 years ago by Andrew Beckett

    1 replies • 14176 views
  • Discussion

    Nested ddt suport

    Category: Mixed-Signal Design

    By Alan21

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    updated over 10 years ago by Andrew Beckett

    1 replies • 14119 views
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