Mixed-Signal Design

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AMS Error: If I insert digital modules, analog circuits are not working as expected, if I delete digital modules, analog circuits are work normally

Category: Mixed-Signal Design

By gordonqd

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updated over 2 years ago by gordonqd

2 replies • 7576 views
Discussion

license problem with xcelium 19.03

Category: Mixed-Signal Design

By Binhngo1210

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started over 2 years ago

0 replies • 7786 views
Discussion

Can you connect an algorithm(MPPT) using veriloga in a boost converter?

Category: Mixed-Signal Design

By Reon

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updated over 2 years ago by Andrew Beckett

2 replies • 1614 views
Discussion

Eye opening center

Category: Mixed-Signal Design

By Kadian

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updated over 2 years ago by Andrew Beckett

5 replies • 8439 views
Discussion

Offset modeling in verilogA

Category: Mixed-Signal Design

By QilongNL

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updated over 2 years ago by Andrew Beckett

2 replies • 8399 views
Discussion

Is it possible to netlist a cross event in Verilog-A?

Category: Mixed-Signal Design

By twix232

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updated over 2 years ago by ShawnLogan

3 replies • 8295 views
Discussion

using "range" in the "Spec" column for the ADEXL Outputs

Category: Mixed-Signal Design

By greywanderer

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updated over 2 years ago by ShawnLogan

3 replies • 3237 views
Discussion

Using $sformat in Verilog AMS

Category: Mixed-Signal Design

By Devin Atkin

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updated over 2 years ago by Devin Atkin

2 replies • 9478 views
Discussion

Using $strobe in Verilog-A module

Category: Mixed-Signal Design

By Brad RFeng

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updated over 2 years ago by Andrew Beckett

13 replies • 13717 views
Discussion

Phase Frequency Detector

Category: Mixed-Signal Design

By parultrivedi

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updated over 2 years ago by Andrew Beckett

3 replies • 10966 views
Discussion

bus values in corners

Category: Mixed-Signal Design

By greywanderer

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updated over 2 years ago by greywanderer

2 replies • 6845 views
Discussion

saving bus of nets within an extracted view

Category: Mixed-Signal Design

By NewScreenName

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updated over 2 years ago by NewScreenName

15 replies • 12939 views
Discussion

cds_global varible errors in config mode

Category: Mixed-Signal Design

By Binhngo1210

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updated over 2 years ago by Binhngo1210

2 replies • 7617 views
Discussion

Measure a branch current in Verilog AMS (Probe Command)

Category: Mixed-Signal Design

By Devin Atkin

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started over 2 years ago

0 replies • 7329 views
Discussion

Modeling transition in SV-RNM

Category: Mixed-Signal Design

By naumel

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started over 2 years ago

0 replies • 6485 views

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