Mixed-Signal Design

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PSS + PNOISE Simulation Problem for the PLL

Category: Mixed-Signal Design

By MtnDew12fl
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updated over 1 year ago by MtnDew12fl

2 replies • 4004 views
Discussion

[Verilog-AMS][Xcelium version]

Category: Mixed-Signal Design

By IssacW
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updated over 1 year ago by IssacW

6 replies • 3716 views
Discussion

Floorplanning Problems in Mixed-Signal Design with Digital Block Pins Optimization

Category: Mixed-Signal Design

By Layouter5338
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started over 1 year ago

0 replies • 3173 views
Discussion

xmelab: *E,CUVHNF error using Xcelium 19.09-s008

Category: Mixed-Signal Design

By markris
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updated over 1 year ago by markris

4 replies • 3310 views
Discussion

Deepprobe within systemverilog hierarchy

Category: Mixed-Signal Design

By NewScreenName
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updated over 1 year ago by NewScreenName

7 replies • 6463 views
Discussion

how to fix the cdl file import error in virtuoso, please expert help on it.

Category: Mixed-Signal Design

By axlrose2138
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started over 1 year ago

0 replies • 3569 views
Discussion

Virtuoso AMS error

Category: Mixed-Signal Design

By Emily157
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updated over 1 year ago by Emily157

7 replies • 6538 views
Discussion

AMS *F,MAXERR: Maximum error count of 50 reached (Total number of errors detected were 50).

Category: Mixed-Signal Design

By nonameirvine
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started over 1 year ago

0 replies • 1198 views
Discussion

Switched capacitance / Variable capacitor

Category: Mixed-Signal Design

By HHOSSAM
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updated over 1 year ago by Frank Wiedmann

1 replies • 4076 views
Discussion

Compile and elaborate problem with VerilogA blocks in AMS simulation

Category: Mixed-Signal Design

By zhaoyu
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started over 1 year ago

0 replies • 4044 views
Discussion

In AMS simulation, how to increase the stop time of the analog solver?

Category: Mixed-Signal Design

By SaranyaBalan
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updated over 1 year ago by tpylant

1 replies • 4334 views
Discussion

Xcelium AMS flow do not support 32bit

Category: Mixed-Signal Design

By stones
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updated over 1 year ago by Andrew Beckett

1 replies • 4522 views
Discussion

Create verilog netlist without simulator license

Category: Mixed-Signal Design

By mikewu999
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updated over 1 year ago by Andrew Beckett

5 replies • 6399 views
Discussion

sampled PAC simulation

Category: Mixed-Signal Design

By Mahdi1364
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started over 1 year ago

0 replies • 4037 views
Discussion

ADE design variable:: evaluate desVar expression/equation to scalar before simulation, in order for the netlist to contain a scalar value instead of an equation.

Category: Mixed-Signal Design

By frankp
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updated over 1 year ago by frankp

7 replies • 3186 views

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