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Mixed-Signal Design

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  • Discussion

    controlling the analog solver within verilog

    Category: Mixed-Signal Design

    By freitas

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    started over 12 years ago

    0 replies • 13390 views
  • Discussion

    about 64 - 32 bit binaries (ultrasim64)

    Category: Mixed-Signal Design

    By Thodoros

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    •

    updated over 12 years ago by Thodoros

    6 replies • 5588 views
  • Discussion

    Designing Digital FIR Filter using Cadence Tools

    Category: Mixed-Signal Design

    By indra0804

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    started over 12 years ago

    0 replies • 15245 views
  • Discussion

    Non-piecewise constant argument is detected in the transition filter.

    Category: Mixed-Signal Design

    By freitas

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    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 14164 views
  • Discussion

    CADENCE capacitor corners max min typ meaning

    Category: Mixed-Signal Design

    By Ricardo Alves

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    updated over 12 years ago by Andrew Beckett

    1 replies • 15250 views
  • Discussion

    NC-Verilog Integration netlister explicitly option

    Category: Mixed-Signal Design

    By Provence

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    updated over 12 years ago by Provence

    3 replies • 16958 views
  • Discussion

    Monto carlo simulation

    Category: Mixed-Signal Design

    By Custom IC Desi

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    updated over 12 years ago by Andrew Beckett

    1 replies • 14148 views
  • Discussion

    component display

    Category: Mixed-Signal Design

    By 40Ford

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    updated over 12 years ago by Sandeep4386

    4 replies • 16505 views
  • Discussion

    Create/Import Verilog-AMS Cell View

    Category: Mixed-Signal Design

    By Bayes

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    updated over 12 years ago by Andrew Beckett

    4 replies • 7781 views
  • Discussion

    How often does AMS flush outputs by default during a simulation?

    Category: Mixed-Signal Design

    By royK

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    updated over 12 years ago by Andrew Beckett

    1 replies • 14487 views
  • Discussion

    AMS Designer & Parameter Arrays

    Category: Mixed-Signal Design

    By MarkusK

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    updated over 12 years ago by MarkusK

    4 replies • 2560 views
  • Discussion

    Problem in Running UltrasimVerilog

    Category: Mixed-Signal Design

    By aarthymani

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    updated over 12 years ago by aarthymani

    5 replies • 15327 views
  • Discussion

    Using (TI) Pspice model in Virtuoso

    Category: Mixed-Signal Design

    By B Josime

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    •

    updated over 12 years ago by B Josime

    4 replies • 15985 views
  • Discussion

    GCC_3.3.1 not found (required by /usr/lib/libX11.so.6

    Category: Mixed-Signal Design

    By KR1089

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    updated over 12 years ago by Andrew Beckett

    1 replies • 805 views
  • Discussion

    error during tran analysis using ams simulator

    Category: Mixed-Signal Design

    By RAMYA1

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    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 13815 views
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