Mixed-Signal Design

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Discussion

Multidimensional Array in Verilog-A

Category: Mixed-Signal Design

By Andrzej
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updated over 3 years ago by Herge

5 replies • 16040 views
Discussion

Extraction failure for Verilog-A due to for loop

Category: Mixed-Signal Design

By UniFleSou
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updated over 3 years ago by UniFleSou

4 replies • 15844 views
Discussion

"Verilog in" setup question and compile *E NOTDIR when use config to open mixed-signal sim bench

Category: Mixed-Signal Design

By Jim0318
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updated over 3 years ago by Jim0318

4 replies • 3987 views
Discussion

Inconsistent Simulation Results

Category: Mixed-Signal Design

By Siona Menezes
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updated over 3 years ago by Andrew Beckett

1 replies • 9141 views
Discussion

Verilog A ADC design

Category: Mixed-Signal Design

By siddafuzzy
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updated over 3 years ago by FormerMember

9 replies • 29605 views
Discussion

Accuracy / Resolution of real variable in SV - AMS simulation beeing limited to 6 bit ?!?!!

Category: Mixed-Signal Design

By JayBee
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updated over 3 years ago by Andrew Beckett

3 replies • 3426 views
Discussion

Annotate currents without adding the outputs to the ADE

Category: Mixed-Signal Design

By AmarDas
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updated over 3 years ago by FormerMember

10 replies • 13468 views
Discussion

error in Transient analysis (SPECTRE-16929)

Category: Mixed-Signal Design

By mirtaji65
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updated over 3 years ago by mirtaji65

2 replies • 11441 views
Discussion

Verilog Stimulus file

Category: Mixed-Signal Design

By ebarajas
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updated over 3 years ago by Andrew Beckett

3 replies • 13020 views
Discussion

Can I pass a variable from ADE Explorer into a systemverilog module as an integer?

Category: Mixed-Signal Design

By BillH314
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started over 3 years ago

0 replies • 9532 views
Discussion

RLC series circuit

Category: Mixed-Signal Design

By vshnkmr
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updated over 3 years ago by FormerMember

5 replies • 11232 views
Discussion

ADDing instances for current source in virtuoso

Category: Mixed-Signal Design

By vshnkmr
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updated over 3 years ago by Andrew Beckett

3 replies • 18507 views
Discussion

Unable to do dc node voltage analysis

Category: Mixed-Signal Design

By vshnkmr
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updated over 3 years ago by Andrew Beckett

5 replies • 11499 views
Discussion

inconsistent xmvlog failure in Virtuoso AMS setup (assembler failure)

Category: Mixed-Signal Design

By monglebest2022
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updated over 3 years ago by Andrew Beckett

4 replies • 12605 views
Discussion

pss simulation issues

Category: Mixed-Signal Design

By Binhngo1210
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updated over 3 years ago by Binhngo1210

2 replies • 11094 views

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