Mixed-Signal Design

Latest Posts

Discussion

Spice to Spectre conversion

Category: Mixed-Signal Design

By sram17

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updated over 4 years ago by sram17

17 replies • 20413 views
Discussion

Running Monte carlo simulations in Process corners(SS,FF..)

Category: Mixed-Signal Design

By Jayanta

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started over 4 years ago

0 replies • 1789 views
Discussion

Set initial value for inputs/outputs for verilog cells in mixed-signal simulation (XCELIUM UNL)

Category: Mixed-Signal Design

By patschouly

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updated over 4 years ago by patschouly

1 replies • 4374 views
Discussion

Verilog-A module instantiating

Category: Mixed-Signal Design

By Jacob Bao

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updated over 4 years ago by Andrew Beckett

5 replies • 23409 views
Discussion

Does xrun support connection module between nettype and logic?

Category: Mixed-Signal Design

By RZAQA

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updated over 4 years ago by Andrew Beckett

1 replies • 2101 views
Discussion

In Cadence simulation how to introduce noise in current source

Category: Mixed-Signal Design

By nisgup

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updated over 4 years ago by Andrew Beckett

9 replies • 20718 views
Discussion

Virtuoso: cloning vs unit cell

Category: Mixed-Signal Design

By AshutoshLayout

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updated over 4 years ago by Andrew Beckett

1 replies • 12031 views
Discussion

Problem with ahdlcmi module library

Category: Mixed-Signal Design

By ID90

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updated over 4 years ago by ID90

4 replies • 12933 views
Discussion

File directory if using GUI

Category: Mixed-Signal Design

By Hazem Al Indari

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updated over 4 years ago by Hazem Al Indari

3 replies • 12523 views
Discussion

Hierarchical calling of VerilogA models

Category: Mixed-Signal Design

By Kulmani

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updated over 4 years ago by Kulmani

4 replies • 13295 views
Discussion

Missing connectLib

Category: Mixed-Signal Design

By p786

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updated over 4 years ago by Andrew Beckett

7 replies • 22294 views
Discussion

getData "noise" not listed in calculator

Category: Mixed-Signal Design

By chrisindallastx

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updated over 4 years ago by chrisindallastx

2 replies • 3030 views
Discussion

Error in RCX in Assura

Category: Mixed-Signal Design

By Jayanta

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updated over 4 years ago by Jayanta

6 replies • 14430 views
Discussion

Convergence Issues causing simulation to Slowdown while using VerilogA models for a PLL-VCO Loop

Category: Mixed-Signal Design

By Kulmani

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updated over 4 years ago by FormerMember

3 replies • 13366 views
Discussion

Sensitivity analysis in ADE XL

Category: Mixed-Signal Design

By Jayanta

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updated over 4 years ago by Andrew Beckett

1 replies • 14532 views

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