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Mixed-Signal Design

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  • Discussion

    runams cannot handle environment variables in cds.lib?

    Category: Mixed-Signal Design

    By zdu89

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    updated over 3 years ago by Andrew Beckett

    4 replies • 10465 views
  • Discussion

    connectRules for multiple power domain

    Category: Mixed-Signal Design

    By DavidLou

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    updated over 3 years ago by DavidLou

    2 replies • 8623 views
  • Discussion

    usage of busset element

    Category: Mixed-Signal Design

    By paulinho

    $usertype

    •

    updated over 3 years ago by paulinho

    1 replies • 9721 views
  • Discussion

    Monte Carlo simulations and returns suspicious results - error in the setup of results?

    Category: Mixed-Signal Design

    By NewScreenName

    $usertype

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    started over 3 years ago

    0 replies • 761 views
  • Discussion

    Combine design variables in ADE assembler

    Category: Mixed-Signal Design

    By NewScreenName

    $usertype

    •

    updated over 3 years ago by NewScreenName

    7 replies • 11576 views
  • Discussion

    Failed to import verilog files

    Category: Mixed-Signal Design

    By Yongqi Hu

    $usertype

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    updated over 3 years ago by Yongqi Hu

    6 replies • 12536 views
  • Discussion

    save current data

    Category: Mixed-Signal Design

    By feixiangzhf

    $usertype

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    updated over 3 years ago by Andrew Beckett

    1 replies • 8170 views
  • Discussion

    Is that possible to write an external function and call it in Virtuoso Verilog-A through VPI

    Category: Mixed-Signal Design

    By HiddenOnee

    $usertype

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    updated over 3 years ago by HiddenOnee

    2 replies • 9228 views
  • Discussion

    xrun simulation elaborates systemverilog real as binary

    Category: Mixed-Signal Design

    By JayBee

    $usertype

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    updated over 3 years ago by JayBee

    1 replies • 9691 views
  • Discussion

    AMS UNL Netlister fails due to bad line breaks in attributes

    Category: Mixed-Signal Design

    By hiddenriver

    $usertype

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    updated over 3 years ago by hiddenriver

    1 replies • 8468 views
  • Discussion

    changes in schematic/sim settings not getting updated.in ams

    Category: Mixed-Signal Design

    By paulinho

    $usertype

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    updated over 3 years ago by paulinho

    2 replies • 2176 views
  • Discussion

    AMS netlister issue

    Category: Mixed-Signal Design

    By Peter321

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    started over 3 years ago

    0 replies • 8006 views
  • Discussion

    Can I do PSS analysis by the AMS simulator in ADE?

    Category: Mixed-Signal Design

    By paulinho

    $usertype

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    updated over 3 years ago by FormerMember

    3 replies • 9790 views
  • Discussion

    Using XCelium instead of Incisive

    Category: Mixed-Signal Design

    By EmanueleI3N

    $usertype

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    started over 3 years ago

    0 replies • 10431 views
  • Discussion

    Asynchronous Ideal ADC in Verilog A in DC simulation

    Category: Mixed-Signal Design

    By Abderezai

    $usertype

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    updated over 3 years ago by talithalinton

    2 replies • 12087 views
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