Mixed-Signal Design

Latest Posts

Discussion

AMS UNL Netlister fails due to bad line breaks in attributes

Category: Mixed-Signal Design

By hiddenriver
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updated over 2 years ago by hiddenriver

1 replies • 7647 views
Discussion

changes in schematic/sim settings not getting updated.in ams

Category: Mixed-Signal Design

By paulinho
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updated over 2 years ago by paulinho

2 replies • 1897 views
Discussion

AMS netlister issue

Category: Mixed-Signal Design

By Peter321
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started over 2 years ago

0 replies • 7247 views
Discussion

Can I do PSS analysis by the AMS simulator in ADE?

Category: Mixed-Signal Design

By paulinho
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updated over 2 years ago by FormerMember

3 replies • 8843 views
Discussion

Using XCelium instead of Incisive

Category: Mixed-Signal Design

By EmanueleI3N
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started over 2 years ago

0 replies • 9295 views
Discussion

Asynchronous Ideal ADC in Verilog A in DC simulation

Category: Mixed-Signal Design

By Abderezai
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updated over 2 years ago by talithalinton

2 replies • 11012 views
Discussion

requesting to help adding model library in spice netlist

Category: Mixed-Signal Design

By sateesh20
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updated over 2 years ago by sateesh20

2 replies • 9953 views
Discussion

vsource will not accept expressions in its parameters

Category: Mixed-Signal Design

By NewScreenName
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updated over 3 years ago by NewScreenName

2 replies • 8104 views
Discussion

How to define current in verilogams-wreal model ?

Category: Mixed-Signal Design

By bikram1994
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updated over 3 years ago by Andrew Beckett

3 replies • 10504 views
Discussion

CDF callback discrepancies between design variables and hard-coded parameter values

Category: Mixed-Signal Design

By VincentCheung
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updated over 3 years ago by VincentCheung

2 replies • 8489 views
Discussion

Array of design variables for an array of Instances

Category: Mixed-Signal Design

By VincentCheung
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updated over 3 years ago by VincentCheung

2 replies • 9210 views
Discussion

ams simulation does not work with large number of design points

Category: Mixed-Signal Design

By delgsy
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updated over 3 years ago by lornagandy

2 replies • 8933 views
Discussion

Issue with simulating Verilog Functional view

Category: Mixed-Signal Design

By AmarDas
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updated over 3 years ago by AmarDas

2 replies • 9183 views
Discussion

Simulating the instance 50 times

Category: Mixed-Signal Design

By AnubhaSehgal
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updated over 3 years ago by Andrew Beckett

3 replies • 8568 views
Discussion

Verilog A: analog event needed to create a decimal to binary block

Category: Mixed-Signal Design

By NewScreenName
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updated over 3 years ago by FormerMember

3 replies • 16569 views

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