Mixed-Signal Design

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Discussion

AMS UNL Netlister fails due to bad line breaks in attributes

Category: Mixed-Signal Design

By hiddenriver

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updated over 3 years ago by hiddenriver

1 replies • 8916 views
Discussion

changes in schematic/sim settings not getting updated.in ams

Category: Mixed-Signal Design

By paulinho

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updated over 3 years ago by paulinho

2 replies • 2296 views
Discussion

AMS netlister issue

Category: Mixed-Signal Design

By Peter321

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started over 3 years ago

0 replies • 8444 views
Discussion

Can I do PSS analysis by the AMS simulator in ADE?

Category: Mixed-Signal Design

By paulinho

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updated over 3 years ago by FormerMember

3 replies • 10312 views
Discussion

Using XCelium instead of Incisive

Category: Mixed-Signal Design

By EmanueleI3N

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started over 3 years ago

0 replies • 11058 views
Discussion

Asynchronous Ideal ADC in Verilog A in DC simulation

Category: Mixed-Signal Design

By Abderezai

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updated over 3 years ago by talithalinton

2 replies • 12651 views
Discussion

requesting to help adding model library in spice netlist

Category: Mixed-Signal Design

By sateesh20

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updated over 3 years ago by sateesh20

2 replies • 11303 views
Discussion

vsource will not accept expressions in its parameters

Category: Mixed-Signal Design

By NewScreenName

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updated over 3 years ago by NewScreenName

2 replies • 9453 views
Discussion

How to define current in verilogams-wreal model ?

Category: Mixed-Signal Design

By bikram1994

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updated over 3 years ago by Andrew Beckett

3 replies • 12064 views
Discussion

CDF callback discrepancies between design variables and hard-coded parameter values

Category: Mixed-Signal Design

By VincentCheung

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updated over 3 years ago by VincentCheung

2 replies • 9866 views
Discussion

Array of design variables for an array of Instances

Category: Mixed-Signal Design

By VincentCheung

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updated over 3 years ago by VincentCheung

2 replies • 10650 views
Discussion

ams simulation does not work with large number of design points

Category: Mixed-Signal Design

By delgsy

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updated over 3 years ago by lornagandy

2 replies • 10216 views
Discussion

Issue with simulating Verilog Functional view

Category: Mixed-Signal Design

By AmarDas

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updated over 3 years ago by AmarDas

2 replies • 10566 views
Discussion

Simulating the instance 50 times

Category: Mixed-Signal Design

By AnubhaSehgal

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updated over 3 years ago by Andrew Beckett

3 replies • 9878 views
Discussion

Verilog A: analog event needed to create a decimal to binary block

Category: Mixed-Signal Design

By NewScreenName

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updated over 3 years ago by FormerMember

3 replies • 18715 views

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