Mixed-Signal Design

Latest Posts

Discussion

Combine design variables in ADE assembler

Category: Mixed-Signal Design

By NewScreenName
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updated over 3 years ago by NewScreenName

7 replies • 13296 views
Discussion

Failed to import verilog files

Category: Mixed-Signal Design

By Yongqi Hu
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updated over 3 years ago by Yongqi Hu

6 replies • 14464 views
Discussion

save current data

Category: Mixed-Signal Design

By feixiangzhf
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updated over 3 years ago by Andrew Beckett

1 replies • 9183 views
Discussion

Is that possible to write an external function and call it in Virtuoso Verilog-A through VPI

Category: Mixed-Signal Design

By HiddenOnee
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updated over 3 years ago by HiddenOnee

2 replies • 10392 views
Discussion

xrun simulation elaborates systemverilog real as binary

Category: Mixed-Signal Design

By JayBee
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updated over 3 years ago by JayBee

1 replies • 11112 views
Discussion

AMS UNL Netlister fails due to bad line breaks in attributes

Category: Mixed-Signal Design

By hiddenriver
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updated over 3 years ago by hiddenriver

1 replies • 9551 views
Discussion

changes in schematic/sim settings not getting updated.in ams

Category: Mixed-Signal Design

By paulinho
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updated over 3 years ago by paulinho

2 replies • 2529 views
Discussion

AMS netlister issue

Category: Mixed-Signal Design

By Peter321
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started over 3 years ago

0 replies • 9074 views
Discussion

Can I do PSS analysis by the AMS simulator in ADE?

Category: Mixed-Signal Design

By paulinho
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updated over 3 years ago by FormerMember

3 replies • 11120 views
Discussion

Using XCelium instead of Incisive

Category: Mixed-Signal Design

By EmanueleI3N
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started over 3 years ago

0 replies • 11936 views
Discussion

Asynchronous Ideal ADC in Verilog A in DC simulation

Category: Mixed-Signal Design

By Abderezai
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updated over 3 years ago by talithalinton

2 replies • 13514 views
Discussion

requesting to help adding model library in spice netlist

Category: Mixed-Signal Design

By sateesh20
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updated over 3 years ago by sateesh20

2 replies • 11998 views
Discussion

vsource will not accept expressions in its parameters

Category: Mixed-Signal Design

By NewScreenName
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updated over 3 years ago by NewScreenName

2 replies • 10139 views
Discussion

How to define current in verilogams-wreal model ?

Category: Mixed-Signal Design

By bikram1994
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updated over 3 years ago by Andrew Beckett

3 replies • 12840 views
Discussion

CDF callback discrepancies between design variables and hard-coded parameter values

Category: Mixed-Signal Design

By VincentCheung
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updated over 3 years ago by VincentCheung

2 replies • 10538 views

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