Mixed-Signal Design

Latest Posts

Discussion

Array of design variables for an array of Instances

Category: Mixed-Signal Design

By VincentCheung
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updated over 3 years ago by VincentCheung

2 replies • 11336 views
Discussion

ams simulation does not work with large number of design points

Category: Mixed-Signal Design

By delgsy
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updated over 3 years ago by lornagandy

2 replies • 10829 views
Discussion

Issue with simulating Verilog Functional view

Category: Mixed-Signal Design

By AmarDas
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updated over 3 years ago by AmarDas

2 replies • 11263 views
Discussion

Simulating the instance 50 times

Category: Mixed-Signal Design

By AnubhaSehgal
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updated over 3 years ago by Andrew Beckett

3 replies • 10505 views
Discussion

Verilog A: analog event needed to create a decimal to binary block

Category: Mixed-Signal Design

By NewScreenName
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updated over 3 years ago by FormerMember

3 replies • 19906 views
Discussion

How to define a current measurement in ADEXL + Montecarlo using AMS Designer

Category: Mixed-Signal Design

By markris
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updated over 3 years ago by markris

13 replies • 17297 views
Discussion

Allowed amount of input wreal data type

Category: Mixed-Signal Design

By marzi
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updated over 3 years ago by marzi

6 replies • 13485 views
Discussion

Apply Input to array in Cadence virtuoso

Category: Mixed-Signal Design

By AnubhaSehgal
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updated over 3 years ago by AnubhaSehgal

2 replies • 11483 views
Discussion

VerilogA: analysis function will not take a string variable

Category: Mixed-Signal Design

By NewScreenName
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updated over 4 years ago by NewScreenName

4 replies • 12078 views
Discussion

corner column not appearing in ViVa

Category: Mixed-Signal Design

By bnevins
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updated over 4 years ago by bnevins

7 replies • 13367 views
Discussion

How to work with two different GLS netlist which contain same name sub cells in a chiptop AMS simulation?

Category: Mixed-Signal Design

By bikram1994
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started over 4 years ago

0 replies • 9616 views
Discussion

For ADE Assembler, is there an option to "Save simulation data" on specific nets for transient simulation?

Category: Mixed-Signal Design

By UniFleSou
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updated over 4 years ago by UniFleSou

2 replies • 5239 views
Discussion

Priority of netlister when a verilog file is included by AMS Netlister options vs. config view

Category: Mixed-Signal Design

By Johanny Saenz
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updated over 4 years ago by allenmessina

2 replies • 11294 views
Discussion

Where is the location of ams simulator which to be put in its path?

Category: Mixed-Signal Design

By delgsy
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updated over 4 years ago by delgsy

4 replies • 11943 views
Discussion

ERROR (HED-1073) and ERROR (OSSHNL-911) when simulating vhdl + analog blocks

Category: Mixed-Signal Design

By delgsy
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started over 4 years ago

0 replies • 10745 views

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