Mixed-Signal Design

Latest Posts

Discussion

For ADE Assembler, is there an option to "Save simulation data" on specific nets for transient simulation?

Category: Mixed-Signal Design

By UniFleSou

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updated over 3 years ago by UniFleSou

2 replies • 4555 views
Discussion

Priority of netlister when a verilog file is included by AMS Netlister options vs. config view

Category: Mixed-Signal Design

By Johanny Saenz

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updated over 3 years ago by allenmessina

2 replies • 10119 views
Discussion

Where is the location of ams simulator which to be put in its path?

Category: Mixed-Signal Design

By delgsy

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updated over 3 years ago by delgsy

4 replies • 10616 views
Discussion

ERROR (HED-1073) and ERROR (OSSHNL-911) when simulating vhdl + analog blocks

Category: Mixed-Signal Design

By delgsy

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started over 3 years ago

0 replies • 9645 views
Discussion

What is the right format of "Subcircuit file" for defining "scasubckt" cell in "analogLib" library?

Category: Mixed-Signal Design

By fireonthesee88

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updated over 3 years ago by FormerMember

6 replies • 5222 views
Discussion

Xcelium version for cosim

Category: Mixed-Signal Design

By paulinho

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updated over 3 years ago by Andrew Beckett

1 replies • 9895 views
Discussion

How to add ELDO simulator in cadence virtuoso?

Category: Mixed-Signal Design

By sateesh20

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updated over 3 years ago by Andrew Beckett

1 replies • 10087 views
Discussion

Processing ADC digital output

Category: Mixed-Signal Design

By threenca

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updated over 3 years ago by FormerMember

3 replies • 14394 views
Discussion

How to see all the running simulation?

Category: Mixed-Signal Design

By bikram1994

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updated over 3 years ago by Andrew Beckett

3 replies • 10499 views
Discussion

DC sweep and transient at same time

Category: Mixed-Signal Design

By atulkumar245

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updated over 3 years ago by Andrew Beckett

5 replies • 13508 views
Discussion

verilogams $rdist_normal for random resistor value in a transient simulation

Category: Mixed-Signal Design

By AndyD93

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updated over 3 years ago by AndyD93

14 replies • 17766 views
Discussion

how to create a random seed in verilogams with $random

Category: Mixed-Signal Design

By Pedro P

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updated over 3 years ago by Andrew Beckett

3 replies • 14316 views
Discussion

Module instance name changed to hdl_xx when creating verilog netlist

Category: Mixed-Signal Design

By YB36

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updated over 3 years ago by Andrew Beckett

5 replies • 12153 views
Discussion

How to read output of a 32bit bus in a transient simulation using Spectre ?

Category: Mixed-Signal Design

By Mdad

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updated over 3 years ago by FormerMember

11 replies • 15642 views
Discussion

The SNR of real signals are degrading in system Verilog model compare to analog signals

Category: Mixed-Signal Design

By bikram1994

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updated over 3 years ago by bikram1994

3 replies • 11203 views

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