Mixed-Signal Design

Latest Posts

Discussion

What is the right format of "Subcircuit file" for defining "scasubckt" cell in "analogLib" library?

Category: Mixed-Signal Design

By fireonthesee88
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updated over 4 years ago by FormerMember

6 replies • 6168 views
Discussion

Xcelium version for cosim

Category: Mixed-Signal Design

By paulinho
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updated over 4 years ago by Andrew Beckett

1 replies • 11016 views
Discussion

How to add ELDO simulator in cadence virtuoso?

Category: Mixed-Signal Design

By sateesh20
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updated over 4 years ago by Andrew Beckett

1 replies • 11166 views
Discussion

Processing ADC digital output

Category: Mixed-Signal Design

By threenca
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updated over 4 years ago by FormerMember

3 replies • 16215 views
Discussion

How to see all the running simulation?

Category: Mixed-Signal Design

By bikram1994
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updated over 4 years ago by Andrew Beckett

3 replies • 11774 views
Discussion

DC sweep and transient at same time

Category: Mixed-Signal Design

By atulkumar245
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updated over 4 years ago by Andrew Beckett

5 replies • 15124 views
Discussion

verilogams $rdist_normal for random resistor value in a transient simulation

Category: Mixed-Signal Design

By AndyD93
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updated over 4 years ago by AndyD93

14 replies • 20176 views
Discussion

how to create a random seed in verilogams with $random

Category: Mixed-Signal Design

By Pedro P
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updated over 4 years ago by Andrew Beckett

3 replies • 16104 views
Discussion

Module instance name changed to hdl_xx when creating verilog netlist

Category: Mixed-Signal Design

By YB36
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updated over 4 years ago by Andrew Beckett

5 replies • 13757 views
Discussion

How to read output of a 32bit bus in a transient simulation using Spectre ?

Category: Mixed-Signal Design

By Mdad
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updated over 4 years ago by FormerMember

11 replies • 17793 views
Discussion

The SNR of real signals are degrading in system Verilog model compare to analog signals

Category: Mixed-Signal Design

By bikram1994
•
updated over 4 years ago by bikram1994

3 replies • 12410 views
Discussion

Cadence virtuoso Vs. ADS

Category: Mixed-Signal Design

By Hammam
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updated over 4 years ago by Andrew Beckett

2 replies • 14837 views
Discussion

How to Model a Filter in VerilogA other than laplace function?

Category: Mixed-Signal Design

By bikram1994
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updated over 4 years ago by Andrew Beckett

3 replies • 14401 views
Discussion

How to create vhdl view and symbol from an existing vhdl cdoe?

Category: Mixed-Signal Design

By bikram1994
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updated over 4 years ago by bikram1994

2 replies • 13144 views
Discussion

Segmentation fault error with increased time of transient simulation and errerorpreset

Category: Mixed-Signal Design

By RFStuff
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updated over 4 years ago by Andrew Beckett

1 replies • 11601 views

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