Mixed-Signal Design

Latest Posts

Discussion

How to include a verilog file/functional view in HED?

Category: Mixed-Signal Design

By Johanny Saenz

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updated over 3 years ago by Frank Wiedmann

8 replies • 7460 views
Discussion

Instantiating a schematic in a verilog-a module

Category: Mixed-Signal Design

By DanteCpp

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updated over 3 years ago by DanteCpp

6 replies • 16527 views
Discussion

Cadence Virtuoso Result plot - slope change point

Category: Mixed-Signal Design

By asrf

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updated over 3 years ago by asrf

5 replies • 5238 views
Discussion

Using dyn_floatdcpath in AMS Simulations

Category: Mixed-Signal Design

By baltacican87

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updated over 3 years ago by baltacican87

4 replies • 11289 views
Discussion

Noisy ac analysis result at low frequency

Category: Mixed-Signal Design

By eyalg

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updated over 3 years ago by Frank Wiedmann

8 replies • 16007 views
Discussion

Assignment of wreal nets without using ports

Category: Mixed-Signal Design

By CharlesMyers

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started over 3 years ago

0 replies • 9730 views
Discussion

Loading third party shared libraries needed by custom C-code function used in Verilog-A with CDS_VA_DPI

Category: Mixed-Signal Design

By Herge

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updated over 3 years ago by Andrew Beckett

3 replies • 10707 views
Discussion

Technical guidance on Cadence-Python Co-simulation

Category: Mixed-Signal Design

By VLSI lab IITB

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updated over 3 years ago by Andrew Beckett

2 replies • 13298 views
Discussion

verilog AMS sine wave generator

Category: Mixed-Signal Design

By praseetha

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updated over 3 years ago by praseetha

4 replies • 15934 views
Discussion

Multidimensional Array in Verilog-A

Category: Mixed-Signal Design

By Andrzej

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updated over 3 years ago by Herge

5 replies • 17341 views
Discussion

Extraction failure for Verilog-A due to for loop

Category: Mixed-Signal Design

By UniFleSou

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updated over 3 years ago by UniFleSou

4 replies • 17341 views
Discussion

"Verilog in" setup question and compile *E NOTDIR when use config to open mixed-signal sim bench

Category: Mixed-Signal Design

By Jim0318

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updated over 3 years ago by Jim0318

4 replies • 4466 views
Discussion

Inconsistent Simulation Results

Category: Mixed-Signal Design

By Siona Menezes

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updated over 4 years ago by Andrew Beckett

1 replies • 9925 views
Discussion

Verilog A ADC design

Category: Mixed-Signal Design

By siddafuzzy

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updated over 4 years ago by FormerMember

9 replies • 31205 views
Discussion

Accuracy / Resolution of real variable in SV - AMS simulation beeing limited to 6 bit ?!?!!

Category: Mixed-Signal Design

By JayBee

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updated over 4 years ago by Andrew Beckett

3 replies • 3798 views

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