Mixed-Signal Design

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Discussion

Co-simulation issue: The S-Function for SimulinkCoupler does not exist"

Category: Mixed-Signal Design

By Alexandar
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updated over 4 years ago by Andrew Beckett

1 replies • 2466 views
Discussion

Accurate sampling (or scheduling an accurante time event) in SPECTRE

Category: Mixed-Signal Design

By RFStuff
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updated over 4 years ago by Andrew Beckett

5 replies • 14186 views
Discussion

Issue in Transition Filter transient slope settings in Verilog-A model

Category: Mixed-Signal Design

By RFStuff
•
updated over 4 years ago by Andrew Beckett

1 replies • 12097 views
Discussion

AMS transient simulation does not run beyond 7000s

Category: Mixed-Signal Design

By RFStuff
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updated over 4 years ago by Andrew Beckett

3 replies • 13265 views
Discussion

Plotting tool

Category: Mixed-Signal Design

By atulkumar245
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updated over 4 years ago by Andrew Beckett

3 replies • 11530 views
Discussion

None of the tools are launching

Category: Mixed-Signal Design

By syasir1
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updated over 4 years ago by Andrew Beckett

3 replies • 11843 views
Discussion

Verilog A frequency calculation

Category: Mixed-Signal Design

By atulkumar245
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updated over 4 years ago by Andrew Beckett

3 replies • 14863 views
Discussion

Virtuoso windows are not coming to the front

Category: Mixed-Signal Design

By VysakhK
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updated over 4 years ago by Andrew Beckett

1 replies • 11779 views
Discussion

Error with installation of lattest IC618 ISR [virtuoso: relocation error: /lib64/libssl.so: symbol private_ossl_minimum_dh_bits, version libcrypto.so.10 not defined in file libcrypto.so.10 with link time reference]

Category: Mixed-Signal Design

By RFStuff
•
updated over 4 years ago by RFStuff

2 replies • 6468 views
Discussion

*ERROR* (AMS-1247): AMS UNL netlisting has failed --> With XCELIUM21.09

Category: Mixed-Signal Design

By RFStuff
•
updated over 4 years ago by RFStuff

5 replies • 7383 views
Discussion

How to know whether we have the valid license of Xcelium

Category: Mixed-Signal Design

By RFStuff
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updated over 4 years ago by Andrew Beckett

1 replies • 13129 views
Discussion

How to include a verilog file/functional view in HED?

Category: Mixed-Signal Design

By Johanny Saenz
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updated over 4 years ago by Frank Wiedmann

8 replies • 8668 views
Discussion

Instantiating a schematic in a verilog-a module

Category: Mixed-Signal Design

By DanteCpp
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updated over 4 years ago by DanteCpp

6 replies • 18597 views
Discussion

Cadence Virtuoso Result plot - slope change point

Category: Mixed-Signal Design

By asrf
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updated over 4 years ago by asrf

5 replies • 6165 views
Discussion

Using dyn_floatdcpath in AMS Simulations

Category: Mixed-Signal Design

By baltacican87
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updated over 4 years ago by baltacican87

4 replies • 12608 views

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