Mixed-Signal Design

Latest Posts

Discussion

Noisy ac analysis result at low frequency

Category: Mixed-Signal Design

By eyalg
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updated over 4 years ago by Frank Wiedmann

8 replies • 17594 views
Discussion

Assignment of wreal nets without using ports

Category: Mixed-Signal Design

By CharlesMyers
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started over 4 years ago

0 replies • 10730 views
Discussion

Loading third party shared libraries needed by custom C-code function used in Verilog-A with CDS_VA_DPI

Category: Mixed-Signal Design

By Herge
•
updated over 4 years ago by Andrew Beckett

3 replies • 11881 views
Discussion

Technical guidance on Cadence-Python Co-simulation

Category: Mixed-Signal Design

By VLSI lab IITB
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updated over 4 years ago by Andrew Beckett

2 replies • 14832 views
Discussion

verilog AMS sine wave generator

Category: Mixed-Signal Design

By praseetha
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updated over 4 years ago by praseetha

4 replies • 17497 views
Discussion

Multidimensional Array in Verilog-A

Category: Mixed-Signal Design

By Andrzej
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updated over 4 years ago by Herge

5 replies • 19384 views
Discussion

Extraction failure for Verilog-A due to for loop

Category: Mixed-Signal Design

By UniFleSou
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updated over 4 years ago by UniFleSou

4 replies • 19402 views
Discussion

"Verilog in" setup question and compile *E NOTDIR when use config to open mixed-signal sim bench

Category: Mixed-Signal Design

By Jim0318
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updated over 4 years ago by Jim0318

4 replies • 5126 views
Discussion

Inconsistent Simulation Results

Category: Mixed-Signal Design

By Siona Menezes
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updated over 4 years ago by Andrew Beckett

1 replies • 10931 views
Discussion

Verilog A ADC design

Category: Mixed-Signal Design

By siddafuzzy
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updated over 4 years ago by FormerMember

9 replies • 33481 views
Discussion

Accuracy / Resolution of real variable in SV - AMS simulation beeing limited to 6 bit ?!?!!

Category: Mixed-Signal Design

By JayBee
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updated over 4 years ago by Andrew Beckett

3 replies • 4264 views
Discussion

Annotate currents without adding the outputs to the ADE

Category: Mixed-Signal Design

By AmarDas
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updated over 4 years ago by FormerMember

10 replies • 16609 views
Discussion

error in Transient analysis (SPECTRE-16929)

Category: Mixed-Signal Design

By mirtaji65
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updated over 4 years ago by mirtaji65

2 replies • 14046 views
Discussion

Verilog Stimulus file

Category: Mixed-Signal Design

By ebarajas
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updated over 4 years ago by Andrew Beckett

3 replies • 16119 views
Discussion

Can I pass a variable from ADE Explorer into a systemverilog module as an integer?

Category: Mixed-Signal Design

By BillH314
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started over 4 years ago

0 replies • 11301 views

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