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Mixed-Signal Design

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  • Discussion

    Cadence Virtuoso Result plot - slope change point

    Category: Mixed-Signal Design

    By asrf

    •

    updated over 4 years ago by asrf

    5 replies • 6579 views
  • Discussion

    Using dyn_floatdcpath in AMS Simulations

    Category: Mixed-Signal Design

    By baltacican87

    •

    updated over 4 years ago by baltacican87

    4 replies • 12778 views
  • Discussion

    Noisy ac analysis result at low frequency

    Category: Mixed-Signal Design

    By eyalg

    •

    updated over 4 years ago by Frank Wiedmann

    8 replies • 17795 views
  • Discussion

    Assignment of wreal nets without using ports

    Category: Mixed-Signal Design

    By CharlesMyers

    •

    started over 4 years ago

    0 replies • 10808 views
  • Discussion

    Loading third party shared libraries needed by custom C-code function used in Verilog-A with CDS_VA_DPI

    Category: Mixed-Signal Design

    By Herge

    •

    updated over 4 years ago by Andrew Beckett

    3 replies • 12006 views
  • Discussion

    Technical guidance on Cadence-Python Co-simulation

    Category: Mixed-Signal Design

    By VLSI lab IITB

    •

    updated over 4 years ago by Andrew Beckett

    2 replies • 15116 views
  • Discussion

    verilog AMS sine wave generator

    Category: Mixed-Signal Design

    By praseetha

    •

    updated over 4 years ago by praseetha

    4 replies • 17701 views
  • Discussion

    Multidimensional Array in Verilog-A

    Category: Mixed-Signal Design

    By Andrzej

    •

    updated over 4 years ago by Herge

    5 replies • 19676 views
  • Discussion

    Extraction failure for Verilog-A due to for loop

    Category: Mixed-Signal Design

    By UniFleSou

    •

    updated over 4 years ago by UniFleSou

    4 replies • 19883 views
  • Discussion

    "Verilog in" setup question and compile *E NOTDIR when use config to open mixed-signal sim bench

    Category: Mixed-Signal Design

    By Jim0318

    •

    updated over 4 years ago by Jim0318

    4 replies • 5398 views
  • Discussion

    Inconsistent Simulation Results

    Category: Mixed-Signal Design

    By Siona Menezes

    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 10998 views
  • Discussion

    Verilog A ADC design

    Category: Mixed-Signal Design

    By siddafuzzy

    •

    updated over 4 years ago by FormerMember

    9 replies • 34181 views
  • Discussion

    Accuracy / Resolution of real variable in SV - AMS simulation beeing limited to 6 bit ?!?!!

    Category: Mixed-Signal Design

    By JayBee

    •

    updated over 4 years ago by Andrew Beckett

    3 replies • 4406 views
  • Discussion

    Annotate currents without adding the outputs to the ADE

    Category: Mixed-Signal Design

    By AmarDas

    •

    updated over 4 years ago by FormerMember

    10 replies • 17022 views
  • Discussion

    error in Transient analysis (SPECTRE-16929)

    Category: Mixed-Signal Design

    By mirtaji65

    •

    updated over 4 years ago by mirtaji65

    2 replies • 14301 views
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