Mixed-Signal Design

Latest Posts

Discussion

RLC series circuit

Category: Mixed-Signal Design

By vshnkmr
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updated over 4 years ago by FormerMember

5 replies • 13578 views
Discussion

ADDing instances for current source in virtuoso

Category: Mixed-Signal Design

By vshnkmr
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updated over 4 years ago by Andrew Beckett

3 replies • 22496 views
Discussion

Unable to do dc node voltage analysis

Category: Mixed-Signal Design

By vshnkmr
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updated over 4 years ago by Andrew Beckett

5 replies • 13736 views
Discussion

inconsistent xmvlog failure in Virtuoso AMS setup (assembler failure)

Category: Mixed-Signal Design

By monglebest2022
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updated over 4 years ago by Andrew Beckett

4 replies • 15537 views
Discussion

pss simulation issues

Category: Mixed-Signal Design

By Binhngo1210
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updated over 4 years ago by Binhngo1210

2 replies • 13301 views
Discussion

Netlist bus naming convention in ADE XL and VCD files

Category: Mixed-Signal Design

By nomart
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started over 4 years ago

0 replies • 12350 views
Discussion

Want to assign a variable for a "string parameter" of veriloga block

Category: Mixed-Signal Design

By fatcat1206
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updated over 4 years ago by sergeiGorbikov

4 replies • 7519 views
Discussion

Different results using AMS simulator vs. Spectre simulator

Category: Mixed-Signal Design

By Bjorn VB
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updated over 4 years ago by FormerMember

8 replies • 23188 views
Discussion

Problem with understanding the noise integration

Category: Mixed-Signal Design

By Phong Phan
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updated over 4 years ago by Phong Phan

2 replies • 15016 views
Discussion

question on dyn_mosv check

Category: Mixed-Signal Design

By RZAQA
•
started over 4 years ago

0 replies • 11157 views
Discussion

PSS failure for a ring VCO

Category: Mixed-Signal Design

By subhadeepdatta
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updated over 4 years ago by FormerMember

4 replies • 15760 views
Discussion

Spice to Spectre conversion

Category: Mixed-Signal Design

By sram17
•
updated over 4 years ago by sram17

17 replies • 23144 views
Discussion

Running Monte carlo simulations in Process corners(SS,FF..)

Category: Mixed-Signal Design

By Jayanta
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started over 4 years ago

0 replies • 1968 views
Discussion

Set initial value for inputs/outputs for verilog cells in mixed-signal simulation (XCELIUM UNL)

Category: Mixed-Signal Design

By patschouly
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updated over 4 years ago by patschouly

1 replies • 4950 views
Discussion

Verilog-A module instantiating

Category: Mixed-Signal Design

By Jacob Bao
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updated over 4 years ago by Andrew Beckett

5 replies • 25888 views

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