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Mixed-Signal Design

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  • Discussion

    How to refer to runs in a mdl loop from outside the loop?

    Category: Mixed-Signal Design

    By szier

    •

    updated over 6 years ago by szier

    2 replies • 16025 views
  • Discussion

    ncelab: *N,DLWTLK

    Category: Mixed-Signal Design

    By ykhuang

    •

    updated over 6 years ago by Saloni Chhabra

    1 replies • 2485 views
  • Discussion

    Setting up AMS simulation using interface elements and UPF file.

    Category: Mixed-Signal Design

    By jbaudino

    •

    updated over 6 years ago by jbaudino

    1 replies • 19743 views
  • Discussion

    altergroup

    Category: Mixed-Signal Design

    By szier

    •

    updated over 6 years ago by szier

    3 replies • 17630 views
  • Discussion

    IP3 Simulation of a Sample and Hold Circuit in Spectre

    Category: Mixed-Signal Design

    By growingmind

    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 20718 views
  • Discussion

    PLL Phase noise simulation in Cadence Virtuoso

    Category: Mixed-Signal Design

    By asrf

    •

    updated over 6 years ago by Andrew Beckett

    3 replies • 29444 views
  • Discussion

    how to setup customized rules file to simulation a circuit with 2 level of voltage 1.8v and 3.3v ?

    Category: Mixed-Signal Design

    By Nhumai

    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 16224 views
  • Discussion

    VCOs with Arbitrary Phase Noise Profile

    Category: Mixed-Signal Design

    By growingmind

    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 16545 views
  • Discussion

    Dynamic Comparator Performance Parameter

    Category: Mixed-Signal Design

    By ashish2

    •

    updated over 6 years ago by FormerMember

    1 replies • 16349 views
  • Discussion

    comparator delay with calculator

    Category: Mixed-Signal Design

    By Bob Mounger

    •

    updated over 6 years ago by ashish2

    4 replies • 20121 views
  • Discussion

    schematic that uses spectre M_TWO_PI unhappy in ams

    Category: Mixed-Signal Design

    By drdanmc

    •

    updated over 6 years ago by Andrew Beckett

    2 replies • 16314 views
  • Discussion

    Layout in cadence

    Category: Mixed-Signal Design

    By Priti gupta

    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 15321 views
  • Discussion

    Which errpreset takes precedence, APS accuracy+speed or tran analysis?

    Category: Mixed-Signal Design

    By FormerMember

    •

    updated over 6 years ago by FormerMember

    10 replies • 17202 views
  • Discussion

    control verilog search path in virtuoso "check"

    Category: Mixed-Signal Design

    By drdanmc

    •

    updated over 6 years ago by drdanmc

    2 replies • 3224 views
  • Discussion

    Best practices for Verilog-a modelling time variant resistance

    Category: Mixed-Signal Design

    By LDIL

    •

    updated over 6 years ago by Frank Wiedmann

    3 replies • 18888 views
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