Mixed-Signal Design

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Discussion

ncelab: *N,DLWTLK

Category: Mixed-Signal Design

By ykhuang
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updated over 6 years ago by Saloni Chhabra

1 replies • 2392 views
Discussion

Setting up AMS simulation using interface elements and UPF file.

Category: Mixed-Signal Design

By jbaudino
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updated over 6 years ago by jbaudino

1 replies • 19295 views
Discussion

altergroup

Category: Mixed-Signal Design

By szier
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updated over 6 years ago by szier

3 replies • 17294 views
Discussion

IP3 Simulation of a Sample and Hold Circuit in Spectre

Category: Mixed-Signal Design

By growingmind
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updated over 6 years ago by Andrew Beckett

1 replies • 20441 views
Discussion

PLL Phase noise simulation in Cadence Virtuoso

Category: Mixed-Signal Design

By asrf
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updated over 6 years ago by Andrew Beckett

3 replies • 28616 views
Discussion

how to setup customized rules file to simulation a circuit with 2 level of voltage 1.8v and 3.3v ?

Category: Mixed-Signal Design

By Nhumai
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updated over 6 years ago by Andrew Beckett

1 replies • 16058 views
Discussion

VCOs with Arbitrary Phase Noise Profile

Category: Mixed-Signal Design

By growingmind
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updated over 6 years ago by Andrew Beckett

1 replies • 16213 views
Discussion

Dynamic Comparator Performance Parameter

Category: Mixed-Signal Design

By ashish2
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updated over 6 years ago by FormerMember

1 replies • 16235 views
Discussion

comparator delay with calculator

Category: Mixed-Signal Design

By Bob Mounger
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updated over 6 years ago by ashish2

4 replies • 19782 views
Discussion

schematic that uses spectre M_TWO_PI unhappy in ams

Category: Mixed-Signal Design

By drdanmc
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updated over 6 years ago by Andrew Beckett

2 replies • 16131 views
Discussion

Layout in cadence

Category: Mixed-Signal Design

By Priti gupta
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updated over 6 years ago by Andrew Beckett

1 replies • 15231 views
Discussion

Which errpreset takes precedence, APS accuracy+speed or tran analysis?

Category: Mixed-Signal Design

By FormerMember
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updated over 6 years ago by FormerMember

10 replies • 16055 views
Discussion

control verilog search path in virtuoso "check"

Category: Mixed-Signal Design

By drdanmc
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updated over 6 years ago by drdanmc

2 replies • 3087 views
Discussion

Best practices for Verilog-a modelling time variant resistance

Category: Mixed-Signal Design

By LDIL
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updated over 6 years ago by Frank Wiedmann

3 replies • 18566 views
Discussion

vector net cannot be connected to a spice/spectre instance by port name

Category: Mixed-Signal Design

By PrasadAMSEng
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updated over 6 years ago by J S Mason

4 replies • 5632 views

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