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Mixed-Signal Design

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  • Discussion

    Virtuoso not plotting digital signals in AMS simulation

    Category: Mixed-Signal Design

    By riahm

    •

    started over 7 years ago

    0 replies • 15542 views
  • Discussion

    AMS simulation with digital simulator on top

    Category: Mixed-Signal Design

    By pvuc

    •

    updated over 7 years ago by pvuc

    2 replies • 17274 views
  • Discussion

    PAM4 Signal using ahdllib or bmslib

    Category: Mixed-Signal Design

    By growingmind

    •

    updated over 7 years ago by Andrew Beckett

    3 replies • 20498 views
  • Discussion

    Using AMS simulation final values as stimulus for RF circuit

    Category: Mixed-Signal Design

    By jslaton

    •

    started over 7 years ago

    0 replies • 14519 views
  • Discussion

    Virtuoso ADEXL cluster(SGE) simulation

    Category: Mixed-Signal Design

    By riahm

    •

    updated over 7 years ago by riahm

    2 replies • 2905 views
  • Discussion

    VHDL view to use in heirarchy editor

    Category: Mixed-Signal Design

    By riahm

    •

    updated over 7 years ago by riahm

    8 replies • 26330 views
  • Discussion

    ncelab: *F,OSDINF: instance 'ABC@XYZ .I27' of design unit 'S2LINVV1D0H' is a leaf instance and is unresolved

    Category: Mixed-Signal Design

    By Nicolas Callens

    •

    started over 7 years ago

    0 replies • 4238 views
  • Discussion

    GMRES solver could not converge to the desired tolerance. Please try to increase krylov_size Error while running Pnoise

    Category: Mixed-Signal Design

    By Munish86

    •

    updated over 7 years ago by Munish86

    4 replies • 19615 views
  • Discussion

    Supply sensitive connect modules vs Dynamic connect modules

    Category: Mixed-Signal Design

    By sansh

    •

    started over 7 years ago

    0 replies • 16272 views
  • Discussion

    how to add Verilog testbench for AMS simulation

    Category: Mixed-Signal Design

    By ntuzxy

    •

    updated over 7 years ago by riahm

    2 replies • 21125 views
  • Discussion

    AMS simulation error reporting

    Category: Mixed-Signal Design

    By lanlin

    •

    updated over 7 years ago by lanlin

    8 replies • 21702 views
  • Discussion

    I want to import with verilog in virtuoso(icfb)

    Category: Mixed-Signal Design

    By JOILEB

    •

    updated over 7 years ago by Andrew Beckett

    5 replies • 5705 views
  • Discussion

    The veriloga code when simulted in cadence shows the following error though all the syntax and identifiers match the accellera. Thanks in advance.

    Category: Mixed-Signal Design

    By Avieee

    •

    updated over 7 years ago by Avieee

    4 replies • 17177 views
  • Discussion

    Weird voltage level in verilogA simulation

    Category: Mixed-Signal Design

    By hafiz2431

    •

    updated over 7 years ago by silviabarnett

    2 replies • 15779 views
  • Discussion

    Missing EEnet connect modules

    Category: Mixed-Signal Design

    By drdanmc

    •

    updated over 7 years ago by Frank Wiedmann

    6 replies • 23461 views
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