Mixed-Signal Design

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Discussion

GMRES solver could not converge to the desired tolerance. Please try to increase krylov_size Error while running Pnoise

Category: Mixed-Signal Design

By Munish86

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updated over 6 years ago by Munish86

4 replies • 18611 views
Discussion

Supply sensitive connect modules vs Dynamic connect modules

Category: Mixed-Signal Design

By sansh

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started over 6 years ago

0 replies • 15544 views
Discussion

how to add Verilog testbench for AMS simulation

Category: Mixed-Signal Design

By ntuzxy

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updated over 6 years ago by riahm

2 replies • 20038 views
Discussion

AMS simulation error reporting

Category: Mixed-Signal Design

By lanlin

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updated over 6 years ago by lanlin

8 replies • 20397 views
Discussion

I want to import with verilog in virtuoso(icfb)

Category: Mixed-Signal Design

By JOILEB

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updated over 6 years ago by Andrew Beckett

5 replies • 5069 views
Discussion

The veriloga code when simulted in cadence shows the following error though all the syntax and identifiers match the accellera. Thanks in advance.

Category: Mixed-Signal Design

By Avieee

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updated over 6 years ago by Avieee

4 replies • 16284 views
Discussion

Weird voltage level in verilogA simulation

Category: Mixed-Signal Design

By hafiz2431

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updated over 6 years ago by silviabarnett

2 replies • 15088 views
Discussion

Missing EEnet connect modules

Category: Mixed-Signal Design

By drdanmc

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updated over 6 years ago by Frank Wiedmann

6 replies • 22121 views
Discussion

How to use AMS design flow with standard cell library?

Category: Mixed-Signal Design

By dogrush

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updated over 6 years ago by BijoyKundu

4 replies • 57777 views
Discussion

Simulation of simple Verilog-AMS testbench failed

Category: Mixed-Signal Design

By pyohayo

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updated over 6 years ago by Andrew Beckett

2 replies • 15722 views
Discussion

Simulating CDL netlist in AMS UNL

Category: Mixed-Signal Design

By mayaAMS

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started over 6 years ago

0 replies • 14893 views
Discussion

Plotting a digital bus as an analog signal

Category: Mixed-Signal Design

By mwb1

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updated over 6 years ago by Andrew Beckett

3 replies • 26395 views
Discussion

I/O libraries required from Cadence?

Category: Mixed-Signal Design

By mohammadalizia

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updated over 6 years ago by Andrew Beckett

1 replies • 1256 views
Discussion

Inbuilt math functions for RNM SV modelling of mixed signal blocks

Category: Mixed-Signal Design

By Shanto

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started over 6 years ago

0 replies • 13930 views
Discussion

How to preserve or define real type connection between blocks when generating systemVerilog netlist from schematics

Category: Mixed-Signal Design

By happyy

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started over 6 years ago

0 replies • 14941 views

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