Mixed-Signal Design

Latest Posts

Discussion

VerilogA Out-of-Module access top level nets?

Category: Mixed-Signal Design

By billnxp

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started over 6 years ago

0 replies • 14959 views
Discussion

Transient noise

Category: Mixed-Signal Design

By AllenD

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started over 6 years ago

0 replies • 13990 views
Discussion

Issues with .cdsinit loading

Category: Mixed-Signal Design

By growingmind

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updated over 6 years ago by Andrew Beckett

1 replies • 15481 views
Discussion

Cadence Virtuoso/Design Framework Compatibility with MATLAB

Category: Mixed-Signal Design

By growingmind

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updated over 6 years ago by Andrew Beckett

3 replies • 3221 views
Discussion

Deleting PSF data in Simulation

Category: Mixed-Signal Design

By growingmind

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updated over 6 years ago by Andrew Beckett

3 replies • 17498 views
Discussion

Optimization of multiple tests in ADE-GXL

Category: Mixed-Signal Design

By Eyad A

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updated over 7 years ago by Andrew Beckett

1 replies • 13998 views
Discussion

Run analogLib/fourier before stop time

Category: Mixed-Signal Design

By twen

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updated over 7 years ago by Andrew Beckett

3 replies • 1982 views
Discussion

CDB to OA PDK Translation Issues

Category: Mixed-Signal Design

By growingmind

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updated over 7 years ago by Andrew Beckett

3 replies • 14901 views
Discussion

define different but related parameters in array of stimuli to ADE

Category: Mixed-Signal Design

By CSCNalu

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updated over 7 years ago by CSCNalu

2 replies • 14734 views
Discussion

Active Mixer Conversion Gain Calculation Issue with the Ports

Category: Mixed-Signal Design

By Mehdi Nasr

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updated over 7 years ago by Andrew Beckett

3 replies • 16217 views
Discussion

SAR ADC Output to MATLAB

Category: Mixed-Signal Design

By growingmind

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updated over 7 years ago by Andrew Beckett

1 replies • 15184 views
Discussion

Overdrive Voltage of a Transistor in Cadence Virtuoso/Spectre

Category: Mixed-Signal Design

By growingmind

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updated over 7 years ago by Andrew Beckett

5 replies • 11198 views
Discussion

Plotting Ids vs Vgs in Cadence of a transistor - Want Y Axis to be Square Root of IDS

Category: Mixed-Signal Design

By growingmind

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updated over 7 years ago by Andrew Beckett

1 replies • 4242 views
Discussion

Problems with AHDL Block Rand Bit Stream in Cadence Virtuoso using Spectre RF

Category: Mixed-Signal Design

By growingmind

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updated over 7 years ago by Andrew Beckett

1 replies • 14408 views
Discussion

Want to add Noise in VPWL source along with ECG signal

Category: Mixed-Signal Design

By mohammadalizia

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updated over 7 years ago by Andrew Beckett

4 replies • 16110 views

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