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Mixed-Signal Design

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  • Discussion

    Simulating CDL netlist in AMS UNL

    Category: Mixed-Signal Design

    By mayaAMS

    •

    started over 7 years ago

    0 replies • 15492 views
  • Discussion

    Plotting a digital bus as an analog signal

    Category: Mixed-Signal Design

    By mwb1

    •

    updated over 7 years ago by Andrew Beckett

    3 replies • 27520 views
  • Discussion

    I/O libraries required from Cadence?

    Category: Mixed-Signal Design

    By mohammadalizia

    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 1339 views
  • Discussion

    Inbuilt math functions for RNM SV modelling of mixed signal blocks

    Category: Mixed-Signal Design

    By Shanto

    •

    started over 7 years ago

    0 replies • 14448 views
  • Discussion

    How to preserve or define real type connection between blocks when generating systemVerilog netlist from schematics

    Category: Mixed-Signal Design

    By happyy

    •

    started over 7 years ago

    0 replies • 15513 views
  • Discussion

    Reading values from struct at the input of SystemVerilog model using AMS simulator.

    Category: Mixed-Signal Design

    By stagro

    •

    started over 7 years ago

    0 replies • 15923 views
  • Discussion

    Using systemVerilog files with AMS simulator

    Category: Mixed-Signal Design

    By forXTer

    •

    updated over 7 years ago by Andrew Beckett

    7 replies • 29646 views
  • Discussion

    measurements on eyediagram

    Category: Mixed-Signal Design

    By vamshiky

    •

    updated over 7 years ago by vamshiky

    8 replies • 21519 views
  • Discussion

    ams simulator vs spectre: empty schematic view

    Category: Mixed-Signal Design

    By rosinc

    •

    updated over 7 years ago by rosinc

    2 replies • 16863 views
  • Discussion

    Error with Calibre PEX using a certain PDK in Cadence Virtuoso

    Category: Mixed-Signal Design

    By growingmind

    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 19540 views
  • Discussion

    SpiceIn netlist->schematic

    Category: Mixed-Signal Design

    By paulinho

    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 1869 views
  • Discussion

    VerilogA Out-of-Module access top level nets?

    Category: Mixed-Signal Design

    By billnxp

    •

    started over 7 years ago

    0 replies • 15958 views
  • Discussion

    Transient noise

    Category: Mixed-Signal Design

    By AllenD

    •

    started over 7 years ago

    0 replies • 15141 views
  • Discussion

    Issues with .cdsinit loading

    Category: Mixed-Signal Design

    By growingmind

    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 16762 views
  • Discussion

    Cadence Virtuoso/Design Framework Compatibility with MATLAB

    Category: Mixed-Signal Design

    By growingmind

    •

    updated over 7 years ago by Andrew Beckett

    3 replies • 3699 views
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