Mixed-Signal Design

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Discussion

Finding the magnitude of a plot at a particular time.

Category: Mixed-Signal Design

By Charanraj Mohan

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updated over 8 years ago by Charanraj Mohan

2 replies • 14795 views
Discussion

Extracted View Netlisting Issue

Category: Mixed-Signal Design

By MMueller

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started over 8 years ago

0 replies • 13576 views
Discussion

Cadence tool to generate .lib file for Analog modules

Category: Mixed-Signal Design

By anandmohan

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updated over 8 years ago by Andrew Beckett

1 replies • 14823 views
Discussion

AMS Unified Netlister with irun cannot handle negative resistance

Category: Mixed-Signal Design

By spike

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updated over 8 years ago by Andrew Beckett

3 replies • 15636 views
Discussion

Constraining inputs for digital block in analog-on-top design

Category: Mixed-Signal Design

By JCPR

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started over 8 years ago

0 replies • 13883 views
Discussion

Modulo operation in a decimal-to-binary converter

Category: Mixed-Signal Design

By mixic

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updated over 8 years ago by mixic

2 replies • 21688 views
Discussion

mixed-signal AMS simulation error

Category: Mixed-Signal Design

By apple419

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updated over 8 years ago by Andrew Beckett

11 replies • 24807 views
Discussion

LSF batch jobs are killed on closing ADEXL window

Category: Mixed-Signal Design

By Casp

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updated over 8 years ago by Andrew Beckett

7 replies • 18079 views
Discussion

Where to find frac-N pll workshop pll_zambezi45 and saradc

Category: Mixed-Signal Design

By debaabed

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updated over 8 years ago by debaabed

4 replies • 16424 views
Discussion

Connecting SPICE ports inside a SystemVerilog-only testbench

Category: Mixed-Signal Design

By Pacher Luca

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started over 8 years ago

0 replies • 14019 views
Discussion

where does a layout view get verilog module name from?

Category: Mixed-Signal Design

By drdanmc

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started over 8 years ago

0 replies • 13943 views
Discussion

Assura metal Dummy Fill error with NORMAL Target Hierarchy mode

Category: Mixed-Signal Design

By ManuelSuarez

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started over 8 years ago

0 replies • 13746 views
Discussion

Need to plot the delay of ring oscillator versus input voltage of each stage

Category: Mixed-Signal Design

By Abdhkamal

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updated over 8 years ago by Andrew Beckett

3 replies • 16215 views
Discussion

Current starved delay element

Category: Mixed-Signal Design

By Abdhkamal

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updated over 8 years ago by Andrew Beckett

1 replies • 14969 views
Discussion

Ignoring or avoiding "x" propagtaion for ams simulation for certain signals and/or instances due to connect module definitions

Category: Mixed-Signal Design

By MDiaz

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updated over 8 years ago by Andrew Beckett

3 replies • 4993 views

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