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Mixed-Signal Design

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  • Discussion

    Constraining inputs for digital block in analog-on-top design

    Category: Mixed-Signal Design

    By JCPR

    •

    started over 9 years ago

    0 replies • 14860 views
  • Discussion

    Modulo operation in a decimal-to-binary converter

    Category: Mixed-Signal Design

    By mixic

    •

    updated over 9 years ago by mixic

    2 replies • 23177 views
  • Discussion

    mixed-signal AMS simulation error

    Category: Mixed-Signal Design

    By apple419

    •

    updated over 9 years ago by Andrew Beckett

    11 replies • 27410 views
  • Discussion

    LSF batch jobs are killed on closing ADEXL window

    Category: Mixed-Signal Design

    By Casp

    •

    updated over 9 years ago by Andrew Beckett

    7 replies • 19860 views
  • Discussion

    Where to find frac-N pll workshop pll_zambezi45 and saradc

    Category: Mixed-Signal Design

    By debaabed

    •

    updated over 9 years ago by debaabed

    4 replies • 17661 views
  • Discussion

    Connecting SPICE ports inside a SystemVerilog-only testbench

    Category: Mixed-Signal Design

    By Pacher Luca

    •

    started over 9 years ago

    0 replies • 15017 views
  • Discussion

    where does a layout view get verilog module name from?

    Category: Mixed-Signal Design

    By drdanmc

    •

    started over 9 years ago

    0 replies • 14941 views
  • Discussion

    Assura metal Dummy Fill error with NORMAL Target Hierarchy mode

    Category: Mixed-Signal Design

    By ManuelSuarez

    •

    started over 9 years ago

    0 replies • 14712 views
  • Discussion

    Need to plot the delay of ring oscillator versus input voltage of each stage

    Category: Mixed-Signal Design

    By Abdhkamal

    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 17509 views
  • Discussion

    Current starved delay element

    Category: Mixed-Signal Design

    By Abdhkamal

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 16102 views
  • Discussion

    Ignoring or avoiding "x" propagtaion for ams simulation for certain signals and/or instances due to connect module definitions

    Category: Mixed-Signal Design

    By MDiaz

    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 6003 views
  • Discussion

    noise analysis- regarding

    Category: Mixed-Signal Design

    By Charanraj Mohan

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 2263 views
  • Discussion

    VCO based ADC signal transfer function

    Category: Mixed-Signal Design

    By mohamin

    •

    updated over 9 years ago by mohamin

    2 replies • 18769 views
  • Discussion

    WARNING (ADEXL-2410): Multiple entities....

    Category: Mixed-Signal Design

    By syafiq

    •

    updated over 9 years ago by syafiq

    2 replies • 15082 views
  • Discussion

    unable to plot dB20

    Category: Mixed-Signal Design

    By Charanraj Mohan

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 18715 views
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