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Mixed-Signal Design

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Latest Posts

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  • Discussion

    Saving Selected Variables from Verilog-A module in AMS

    Category: Mixed-Signal Design

    By aarthymani

    •

    started over 11 years ago

    0 replies • 16578 views
  • Discussion

    Testbench using AMS

    Category: Mixed-Signal Design

    By nalini

    •

    started over 11 years ago

    0 replies • 14269 views
  • Discussion

    Dumping waveform in ascii using AMS simulator

    Category: Mixed-Signal Design

    By nalini

    •

    started over 11 years ago

    0 replies • 14683 views
  • Discussion

    while simulating my spectre language code is not showing netlist and showing a bracker is error

    Category: Mixed-Signal Design

    By kunkunuru srik

    •

    started over 11 years ago

    0 replies • 14408 views
  • Discussion

    Cross function

    Category: Mixed-Signal Design

    By analogy

    •

    updated over 11 years ago by Andrew Beckett

    3 replies • 20657 views
  • Discussion

    Help in AMS design and model validation

    Category: Mixed-Signal Design

    By Eman2289

    •

    started over 11 years ago

    0 replies • 14232 views
  • Discussion

    Problem Simulating Verilog-AMS top cellview

    Category: Mixed-Signal Design

    By GabrielB

    •

    updated over 11 years ago by Andrew Beckett

    2 replies • 17848 views
  • Discussion

    About the driving ability of digital circuits in spectreVerilog simulation.

    Category: Mixed-Signal Design

    By xxgenerall

    •

    updated over 11 years ago by xxgenerall

    5 replies • 16277 views
  • Discussion

    netlist differences

    Category: Mixed-Signal Design

    By Ram123

    •

    updated over 11 years ago by Ram123

    2 replies • 15054 views
  • Discussion

    Pin labels in Virtuoso from Encounter OA

    Category: Mixed-Signal Design

    By nevsan

    •

    updated over 11 years ago by nevsan

    5 replies • 20000 views
  • Discussion

    How to instantiate models in verilog-A

    Category: Mixed-Signal Design

    By rajrevanth61

    •

    started over 11 years ago

    0 replies • 14508 views
  • Discussion

    Verilog-a model instantiation

    Category: Mixed-Signal Design

    By rajrevanth61

    •

    started over 11 years ago

    0 replies • 15473 views
  • Discussion

    error while running ADL

    Category: Mixed-Signal Design

    By johannah

    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 14910 views
  • Discussion

    bus value export to table

    Category: Mixed-Signal Design

    By Bob Mounger

    •

    updated over 12 years ago by Bob Mounger

    1 replies • 15065 views
  • Discussion

    NanoRoute crash with incremental tech libraries in mixed signal flow

    Category: Mixed-Signal Design

    By nevsan

    •

    updated over 12 years ago by nevsan

    2 replies • 15528 views
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