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Mixed-Signal Design

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  • Discussion

    Measuring short circuit current (Shoot-through Current)

    Category: Mixed-Signal Design

    By Hagar Hendy

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 6859 views
  • Discussion

    How to see the analog voltage of the output signal of the digital module in AMS simulation

    Category: Mixed-Signal Design

    By wangyunxin

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 7395 views
  • Discussion

    VerilogA blind to DC sweep analysis

    Category: Mixed-Signal Design

    By NewScreenName

    •

    updated over 2 years ago by Andrew Beckett

    11 replies • 13233 views
  • Discussion

    PLL Verification RAK - Total Phase Noise

    Category: Mixed-Signal Design

    By JoJakNap

    •

    updated over 2 years ago by Andrew Beckett

    14 replies • 13239 views
  • Discussion

    AMS simulation IE settings

    Category: Mixed-Signal Design

    By paulinho

    •

    updated over 2 years ago by paulinho

    5 replies • 13862 views
  • Discussion

    Error while running AMS simulations

    Category: Mixed-Signal Design

    By Ann02

    •

    updated over 2 years ago by Andrew Beckett

    3 replies • 8882 views
  • Discussion

    AMS simulation error with bsim bulk model

    Category: Mixed-Signal Design

    By andreschen

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 7008 views
  • Discussion

    How to set a parameter in a Verilog module as a variable, and send it to the ADE Explorer to scan its different values in simulation?

    Category: Mixed-Signal Design

    By wangyunxin

    •

    updated over 2 years ago by Andrew Beckett

    6 replies • 11981 views
  • Discussion

    fixed-point number in simvision

    Category: Mixed-Signal Design

    By wangyunxin

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 7136 views
  • Discussion

    SOA checks across multiple PVT runs

    Category: Mixed-Signal Design

    By NewScreenName

    •

    updated over 2 years ago by ShawnLogan

    5 replies • 11310 views
  • Discussion

    Dinamycally changing accuracy of simulator during runtime

    Category: Mixed-Signal Design

    By NewScreenName

    •

    updated over 2 years ago by NewScreenName

    3 replies • 8687 views
  • Discussion

    how to see value of Verilog variable in ams batch mode simulation?

    Category: Mixed-Signal Design

    By wangyunxin

    •

    updated over 2 years ago by tpylant

    1 replies • 10736 views
  • Discussion

    RTN noise simulation

    Category: Mixed-Signal Design

    By shivaa

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 7316 views
  • Discussion

    Simulate N-bits input configuration in transient

    Category: Mixed-Signal Design

    By IKIF

    •

    updated over 2 years ago by IKIF

    6 replies • 8748 views
  • Discussion

    CML driver phase noise

    Category: Mixed-Signal Design

    By vinodjn

    •

    updated over 2 years ago by ShawnLogan

    11 replies • 13955 views
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