• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      Rita Fung
      Rita Fung 76 Points
    • 2
      AVAQ Semi
      AVAQ Semi 65 Points
    • 3
      ST202606301857
      ST202606301857 50 Points
    • 4
      Electro Node
      Electro Node 42 Points
    • 5
      EDA Star
      EDA Star 41 Points
  • Leaderboard

    • 1
      steve
      steve 17,879 Points
    • 2
      oldmouldy
      oldmouldy 13,840 Points
    • 3
      eDave
      eDave 10,381 Points
    • 4
      ShawnLogan
      ShawnLogan 9,725 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    How to update the netlist (input.scs) from extracted view after QRC extraction

    Category: Custom IC Design

    By Mamad

    •

    updated over 7 years ago by Mamad

    10 replies • 19631 views
  • Discussion

    How to do Components placement movement in a particular angle from existing position when we don't know the exact XY locations to where we need to move

    Category: PCB Design

    By Policharla

    •

    updated over 7 years ago by Tmills

    3 replies • 2113 views
  • Discussion

    ihdl vs netExpr

    Category: Custom IC Design

    By drdanmc

    •

    started over 7 years ago

    0 replies • 15960 views
  • Discussion

    How to use ocnDspfFile with case_sensitive port/net names

    Category: Custom IC SKILL

    By jsundermeyer

    •

    updated over 7 years ago by jsundermeyer

    2 replies • 1349 views
  • Discussion

    Systemverilog interfaces over hierarchical boundaries

    Category: Digital Implementation

    By pvuc

    •

    started over 7 years ago

    0 replies • 16651 views
  • Discussion

    Updating Net Names in Layout XL

    Category: Custom IC Design

    By FormerMember

    •

    updated over 7 years ago by Andrew Beckett

    2 replies • 9198 views
  • Discussion

    Error about Environment Variable settings

    Category: Custom IC SKILL

    By wgtkan

    •

    updated over 7 years ago by wgtkan

    17 replies • 29324 views
  • Discussion

    How to Disable visiblity of only Dynamic Copper shape

    Category: PCB Design

    By chadga

    •

    updated over 7 years ago by chadga

    6 replies • 20319 views
  • Discussion

    How to create custom bus taps

    Category: PCB Design

    By Shells

    •

    started over 7 years ago

    0 replies • 14177 views
  • Discussion

    Parasitic exclusion

    Category: Custom IC Design

    By manudupouy

    •

    updated over 7 years ago by manudupouy

    5 replies • 18967 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information