• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • Site
  • Community Search
  • User
Forum - Thread List
  • Suggested Answer

    trace width showing incorrect value when provided with layer thickness and impedance value 0

    6322 views
    1 reply
    Latest over 2 years ago
    by SandeepVarrier
  • Answered

    DRC error not showing for the unconnected pins 0

    4530 views
    1 reply
    Latest over 2 years ago
    by oldmouldy
  • Not Answered

    OrCAD Capture DRC fails to find unconnected pin even though "Check Unconnected Pins" is selected in DRC rules setup 0

    2982 views
    2 replies
    Latest over 2 years ago
    by RohitRohan
  • Suggested Answer

    3D step file not exporting properly 0

    7665 views
    3 replies
    Latest over 2 years ago
    by JITHINDEV
  • Discussion

    Searching for a component in OrCAD X Capture CIS

    4970 views
    0 replies
    Started over 2 years ago
    by DesignTech
  • Suggested Answer

    Orcad libraries font issues 0

    4693 views
    2 replies
    Latest over 2 years ago
    by Ulf K
  • Suggested Answer

    Making traces skeletal and pads hollow as default whenever opening a design or symbol regardless of its inherited settings? 0

    6354 views
    2 replies
    Latest over 2 years ago
    by Ulf K
  • Answered

    Skill to delete selected net and padstakck via +1

    7640 views
    2 replies
    Latest over 2 years ago
    by zpofrp
  • Not Answered

    Using System Capture in a script (on Linux) 0

    5148 views
    1 reply
    Latest over 2 years ago
    by rg13
  • Suggested Answer

    Error Modifying Part Downloaded from Unified CIS 0

    5149 views
    2 replies
    Latest over 2 years ago
    by rg13
  • Not Answered

    OrCAD 17.4 CIS backannotate pin swap 0

    6018 views
    5 replies
    Latest over 2 years ago
    by RFinley
  • Suggested Answer

    Check no place bound in component 0

    9252 views
    7 replies
    Latest over 2 years ago
    by eDave
  • Suggested Answer

    Facing problem in DRC solution 0

    5520 views
    4 replies
    Latest over 2 years ago
    by HASAN2024
  • Discussion

    How to Improve Relations with your PCB Fabricator with OrCADX Presto LiveDoc

    6144 views
    0 replies
    Started over 2 years ago
    by John T
  • Suggested Answer

    Can't set airgap for pad separation 0

    2051 views
    3 replies
    Latest over 2 years ago
    by JuanCR
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information