• Discussion

  Grids, tabs and forms oh my!

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  1 reply
  Latest over 17 years ago
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• Discussion

  Ver 16.2 -- Highlight where did it go? Locked

  775 views
  2 replies
  Latest over 17 years ago
  by redwire
• Discussion

  NET LIST PROBLEM Locked

  13035 views
  1 reply
  Latest over 17 years ago
  by KeithP
• Discussion

  Encounter SDF file for APR simulation in NC Sim Locked

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  1 reply
  Latest over 17 years ago
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• Discussion

  formatting output depending on length of object

  13142 views
  1 reply
  Latest over 17 years ago
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• Discussion

  clk gating for soc encounter Locked

  14051 views
  2 replies
  Latest over 17 years ago
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• Discussion

  new tech blog on Specman & e Locked

  821 views
  1 reply
  Latest over 17 years ago
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• Discussion

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  4 replies
  Latest over 17 years ago
  by Ejlersen
• Discussion

  Is there a way to check for unplaced schematic symbol versions? Locked

  13144 views
  1 reply
  Latest over 17 years ago
  by steve
• Discussion

  clock tree levels and gating Locked

  16731 views
  6 replies
  Latest over 17 years ago
  by porcupine
• Discussion

  System Verilog Assertions!! Locked

  15283 views
  2 replies
  Latest over 17 years ago
  by ckomar
• Discussion

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  1 reply
  Latest over 17 years ago
  by ARUNKUMAR
• Discussion

  HOW TO UPDATE ECO Locked

  13392 views
  0 replies
  Started over 17 years ago
  by ARUNKUMAR
• Discussion

  long simulation time problem Locked

  15588 views
  1 reply
  Latest over 17 years ago
  by adua
• Discussion

  vhdl-verilog interoperation ? Locked

  18562 views
  6 replies
  Latest over 17 years ago
  by Mickey