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Forum - Thread List
  • Discussion

    using "range" in the "Spec" column for the ADEXL Outputs Locked

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    3 replies
    Latest over 2 years ago
    by ShawnLogan
  • Discussion

    Using $sformat in Verilog AMS Locked

    9982 views
    2 replies
    Latest over 2 years ago
    by Devin Atkin
  • Suggested Answer

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    Latest over 2 years ago
    by B Bruekers
  • Discussion

    Cadence genus synthesis Locked

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    1 reply
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    by DimoM
  • Discussion

    How to create a through separator line in a layout form? Locked

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    Latest over 2 years ago
    by Martinsh
  • Answered

    Cooling - End Wall Holes in Autogrid +1

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    3 replies
    Latest over 2 years ago
    by domen
  • Answered

    Fidelity Split along an ISO curve on primitives 0

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    2 replies
    Latest over 2 years ago
    by nopech
  • Discussion

    NO DC solution found(No convergence) when use ADEXL,but use ADEL is right. Locked

    2308 views
    3 replies
    Latest over 2 years ago
    by Andrew Beckett
  • Discussion

    artwork domain modification via skill?

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    3 replies
    Latest over 2 years ago
    by mir0mik
  • Answered

    PCB SKILL Update Text Using Comment 0

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    6 replies
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    by victorpatrick
  • Discussion

    Using $strobe in Verilog-A module Locked

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    13 replies
    Latest over 2 years ago
    by Andrew Beckett
  • Discussion

    Overview of an IBIS File

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    1 reply
    Latest over 2 years ago
    by SimTech
  • Discussion

    OIF(optimal inductor finder) error Locked

    1540 views
    1 reply
    Latest over 2 years ago
    by Andrew Beckett
  • Discussion

    Spectre warning: there are some nodes and instances from the netlist topology check. Locked

    8137 views
    1 reply
    Latest over 2 years ago
    by Andrew Beckett
  • Not Answered

    Exporting design outline (as DXF or image?) 0

    11468 views
    3 replies
    Latest over 2 years ago
    by Nilanjan Talukder
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