• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    How to run simulations in Explorer/Assembler starting from a netlist? Locked

    5761 views
    8 replies
    Latest over 3 years ago
    by FormerMember
  • Discussion

    Inherited connections and VXL.....again. Locked

    12093 views
    4 replies
    Latest over 3 years ago
    by kenc184
  • Discussion

    How do I set valid layers on bootup of Cadence Virtuoso XL? Locked

    10889 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Not Answered

    Allegro – Tip of the week: Is my database optimized for performance? 0

    8899 views
    0 replies
    Started over 3 years ago
    by PCBTech
  • Discussion

    How to include a verilog file/functional view in HED? Locked

    7420 views
    8 replies
    Latest over 3 years ago
    by Frank Wiedmann
  • Discussion

    Can someone please help with the syntax for a Navigator specific bindkey Locked

    9283 views
    1 reply
    Latest over 3 years ago
    by AurelBuche
  • Discussion

    Automatically loading some libraries into my cds.lib Locked

    12169 views
    1 reply
    Latest over 3 years ago
    by AurelBuche
  • Answered

    Full round shape and route keepout problem 0

    10785 views
    2 replies
    Latest over 3 years ago
    by soll
  • Not Answered

    Align pins of components 0

    12517 views
    5 replies
    Latest over 3 years ago
    by LSAUGE
  • Discussion

    How to find floating metals/vias using skill code Locked

    5056 views
    2 replies
    Latest over 3 years ago
    by prasadtammana
  • Suggested Answer

    Interlayer spacing constraint DRC (detect soldermask layer & silkscreen layer conflict) 0

    3624 views
    3 replies
    Latest over 3 years ago
    by ichliebedich
  • Discussion

    Skill code to generate pins and label on metal by a bindkey Locked

    12911 views
    3 replies
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    Instantiating a schematic in a verilog-a module Locked

    16489 views
    6 replies
    Latest over 3 years ago
    by DanteCpp
  • Not Answered

    Orcad PCB designer Professional crashing 0

    10729 views
    1 reply
    Latest over 3 years ago
    by steve
  • Discussion

    Configuring Toolbar Icons for Custom SKILL Menus

    5349 views
    0 replies
    Started over 3 years ago
    by PCBTech
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information