• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    How much storage does a single simulation use? Locked

    10743 views
    2 replies
    Latest over 4 years ago
    by Holz
  • Discussion

    Same net spacing DRC error handling

    11417 views
    2 replies
    Latest over 4 years ago
    by ichliebedich
  • Not Answered

    How to export a ISCF (Intel Schematic Checking Format) file from 17.2 Cadence/Allegro PCB Designer ? 0

    7282 views
    8 replies
    Latest over 4 years ago
    by luvishis
  • Discussion

    Updating the poly pitch of a transistor Locked

    10323 views
    0 replies
    Started over 4 years ago
    by MSP032
  • Discussion

    Route From Target Hot Key

    10574 views
    3 replies
    Latest over 4 years ago
    by excellon1
  • Discussion

    ADE Assembler Message 1921 - When running multiple sweep points Locked

    8695 views
    6 replies
    Latest over 4 years ago
    by Christos Skoufis
  • Discussion

    recognize paths with metal jumps using DIVA Locked

    10394 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    What is the difference between metal usages and film area in PCB Editor? Locked

    10432 views
    0 replies
    Started over 4 years ago
    by hetban
  • Discussion

    How to remove random Items associating on symbols

    11196 views
    4 replies
    Latest over 4 years ago
    by tmd63
  • Discussion

    Mu and Mu_prime in S parameter analysis Locked

    17062 views
    4 replies
    Latest over 4 years ago
    by Frank Wiedmann
  • Discussion

    How to flatten Pcell in schematic Locked

    13627 views
    3 replies
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    when I run CM Rule, program is down at OrCAD 16.6 latest hotfix (S115) Locked

    10037 views
    0 replies
    Started over 4 years ago
    by ichliebedich
  • Discussion

    How can you move/stretch schematic wires WITHOUT Virtuoso rerouting everything and making a mess? Locked

    5596 views
    2 replies
    Latest over 4 years ago
    by mmsaad66
  • Discussion

    Truncate a List

    13744 views
    4 replies
    Latest over 4 years ago
    by eDave
  • Discussion

    Transient stop time for specified number of clocks Locked

    15270 views
    7 replies
    Latest over 4 years ago
    by Andrew Beckett
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information