• Discussion

  Transfer Layout from Innovus to Virtuoso: Layout pins issue (interoperable between Innovus and Virtuoso using OpenAccess) Locked

  11845 views
  0 replies
  Started over 4 years ago
  by ayande1370
• Not Answered

  ERROR(ORCAP-36055): Illegal character in \ic (logic )\. 0

  25123 views
  9 replies
  Latest over 4 years ago
  by NavyEE
• Discussion

  Error When trying to Import the subcircuit Spice model into Cadence Locked

  22982 views
  9 replies
  Latest over 4 years ago
  by Andrew Beckett
• Discussion

  set default character on FORM input box

  8648 views
  1 reply
  Latest over 4 years ago
  by B Bruekers
• Discussion

  Can I use a variable as interpolation point in the value function? Locked

  15261 views
  5 replies
  Latest over 4 years ago
  by maaz2020
• Discussion

  How to see current color192 state by skill code?

  10909 views
  5 replies
  Latest over 4 years ago
  by mir0mik
• Discussion

  straight line (best) fit using viva calculator Locked

  31943 views
  18 replies
  Latest over 4 years ago
  by Hannahyrh
• Discussion

  Concatenated vectors of strings are truncated when the circuit is being graphed by a measurement, but vectors of integers work fine. Locked

  9229 views
  5 replies
  Latest over 4 years ago
  by FormerMember
• Discussion

  What is the Cadence PSpice equation describing the S switch Locked

  12166 views
  1 reply
  Latest over 4 years ago
  by SZiel
• Discussion

  Issue with axlTriggerSet for double opening

  8422 views
  1 reply
  Latest over 4 years ago
  by mir0mik
• Discussion

  Using wave spec for model validation Locked

  12767 views
  3 replies
  Latest over 4 years ago
  by juanbaudino
• Discussion

  leMergeShapes alternative for PCELL code (compatible with steam-out) Locked

  12587 views
  4 replies
  Latest over 4 years ago
  by Sheppie
• Discussion

  How to Save selected ADHL variable in VarilogA Model Locked

  14730 views
  2 replies
  Latest over 4 years ago
  by AlbertoLopez
• Discussion

  xmsim: *F,RNAERR: The simulator terminated with an analog initialization error. Locked

  5126 views
  4 replies
  Latest over 4 years ago
  by Pedro P
• Discussion

  Verilog-AMS Simulation speed issue while using $table_model for reading from a file. Locked

  11315 views
  1 reply
  Latest over 4 years ago
  by Andrew Beckett