• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    deRegApp doesn't work Locked

    1421 views
    4 replies
    Latest over 1 year ago
    by XY202503208123
  • Not Answered

    Does AWR have a tool that automatically converts lumped element inductor to transmission line? 0

    5020 views
    5 replies
    Latest over 1 year ago
    by OscPn
  • Suggested Answer

    How to fix this power plane discrepancy when exporting odb++ from brd 0

    4890 views
    9 replies
    Latest over 1 year ago
    by EA202507041851
  • Discussion

    Illegal argument for signal access function [4.3(AMSLRM)]. Verilog AMS error. Locked

    1718 views
    1 reply
    Latest over 1 year ago
    by Saloni Chhabra
  • Suggested Answer

    Import Logic/Netlist using SKILL 0

    4365 views
    5 replies
    Latest over 1 year ago
    by Hoangkhoipcb
  • Discussion

    create DSPF/SPICE cellView using SKILL Locked

    3179 views
    6 replies
    Latest over 1 year ago
    by Andrew Beckett
  • Not Answered

    Issue with power planes when exporting ODB++ from BRD 0

    3064 views
    2 replies
    Latest over 1 year ago
    by EA202507041851
  • Not Answered

    Via placement issues on simple DOE 0

    2712 views
    1 reply
    Latest over 1 year ago
    by Elecguy
  • Not Answered

    Implementing a selection tool in SKILL (mimicking Allegro) 0

    1435 views
    1 reply
    Latest over 1 year ago
    by Elecguy
  • Discussion

    How to apply the instance name used in the schematic to the same mosfet in layout? Locked

    7107 views
    10 replies
    Latest over 1 year ago
    by MB202506119828
  • Discussion

    Results from PSF files are out of order Locked

    3525 views
    2 replies
    Latest over 1 year ago
    by Andrew Beckett
  • Discussion

    IC problem in simulation Locked

    3684 views
    3 replies
    Latest over 1 year ago
    by Andrew Beckett
  • Discussion

    How can i make auto y-axis range work for each result in Corner simulation? Locked

    2874 views
    1 reply
    Latest over 1 year ago
    by Andrew Beckett
  • Discussion

    How to exclude subckt ports in certain hierarchy branches? Locked

    2764 views
    1 reply
    Latest over 1 year ago
    by Andrew Beckett
  • Discussion

    Veto variable permutations in Maestro Locked

    3259 views
    3 replies
    Latest over 1 year ago
    by Andrew Beckett
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information