Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Analog/Custom Design: A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

paragb

The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react to a Pcell, but Pcell code should not react to, interact with, or be dependent on an environment. Although it is possible…
- 16 May 2012
Verification: How Debug Breakthroughs are Enabled by In-Circuit Acceleration

fschirrmeister

We in product management are often accused of jumping the gun and announcing products too fast. Users are looking at press releases and are wondering "sounds great, but does it really work?" Cadence announced earlier this week new in-circui...
- 16 May 2012
System, PCB, & Package Design : What's Good About Allegro GRE 2 Point Flow? It’s in the 16.5 Release!

Jerry GenPart
The 16.5 Allegro Global Route Environment (GRE) has been enhanced by what we call a 2 Point Flow. These flows provide the benefit of both a guided flow and the simplicity of a default flow.
The 2 Point Flow:
Provides the benefits of a default flow - no path between the gather points
Provides the guidance that is needed - liberty to exit in the direction of choice
For example, if you wish to provide 'no' guidance to some bundles…
- 15 May 2012
Verification: The Facts: Why Accelerated VIP Is Needed for SoC Verification

PeteHeller

On Tuesday May 15^th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question. This blog will answer that and explain the rationale behind Cadence's AVIP and more about our products and plans going…
- 15 May 2012
Digital Design: Adding Custom Shapes and Text is New and Improved in EDI System 11

wally1

You may have noticed that in the Encounter Digital Implementation (EDI) System 11 the commands addCustomBox, addCustomLine and addCustomText are no longer in the documentation. These previous commands weren't cutting it when it came to the features customers wanted and were not supported by OpenAccess or database commands like dbGet. So they've been replaced in EDI 11 by the commands add_shape and add_text. I think you…
- 14 May 2012
Verification: American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working On!

fschirrmeister

I think all of us engineers have faced at one point or another the need to explain to our parents or friends what we are actually working on. Hey Mom, EDA is where electronics begins! Without us electronics would not change our day to day l...
- 14 May 2012
Verification: DAC 2012 Preview: Focus on Formal and ABV Events and Papers

TeamVerify

In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA), and Team Verify and our colleagues on the Incisive Verification team will be there in force with detailed briefings, panels, papers, posters, and of course live demos in the Cadence booth. Here are the formal and assertion-based verification (ABV) specific highlights:

* On the show floor Monday June 4 through Wednesday June 6, our main…
- 14 May 2012
Verification: Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)

teamspecman

Memory management is not something the Specman user is supposed to worry about. Nobody likes to make notes about allocations and freeing up memory segments when he's programming, and Specman supplies a mechanism that allows the programmer to have some extra time for a cup of coffee.
Unfortunately, in some occasions, this cup of coffee will be very much needed in order to debug why Specman managed the memory this way…
- 11 May 2012
Verification: Video Tech Tip: Data Path Verification Using a Formal Scoreboard with Incisive Formal Verifier

TeamVerify

This 6 minute video is a quick overview of our formal scoreboard app. Specifically, the video references the same AXI bridge example included with Incisive Formal Verifier (IFV) and Incisive Enterprise Verifier (IEV) so you can follow along on your workstation!
If video does not open, click here.
If you want even more background on this app, I invite you to watch the webinar recording on this topic, "Quickly Find Data Transport…
- 8 May 2012
System, PCB, & Package Design : What's Good About Allegro PCB Router HDI Capabilities? 16.5 Has a Few New Enhancements!

Jerry GenPart

More high-density interconnect (HDI) improvements including the tuning of the auto-router (Allegro PCB Router - SPECCTRA) to use the via patterns, alignment of via list priority with Allegro PCB Editor, and creation and removal of anti-acid bars are available in the 16.5 release of the Allegro PCB Router.
Read on for more details…

In this release, the SPECCTRA auto-router provides the ability to use inset/tangency…
- 8 May 2012
System, PCB, & Package Design : Free PCB Signal Integrity Education from Robert Hanson Continues at Cadence in Austin

TeamAllegro

Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last month where they were greeted by world renowned signal integrity educator Robert Hanson. Robert spent two full days taking them from the basics of transmission line theory all the way through the challenging aspects of compliance of serial interface standards running at 8 gigabits per second. And if that was not enough, he then went into…
- 8 May 2012
Verification: Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox

jasona

In my last blog post, I covered three frequently asked questions about using the Xilinx Zynq-7000 Virtual Platform as a VirtualBox appliance. Today, I'll cover the next most frequently asked question. It is related to simulation performance. This...
- 7 May 2012
Verification: Xilinx Zynq-7000 Virtual Platform Frequently Asked Questions: VirtualBox Edition

jasona

The use of virtual machine technology offers great ease of use benefits. Since the virtual platform for the Xilinx Zynq-7000 Extensible Processing Platform has been available as a virtual machine appliance, I have seen it run by many people&nbsp...
- 2 May 2012
Digital Design: Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Directory

Kari

No matter how you run your power analysis - with Encounter Power System (EPS) or from within Encounter Digital Implementation (EDI) System - you're probably familiar with the result directory. It will look something like VDD_125C_avg_1 and have lots of files inside. The first ones you probably look at are the "results" text file and the ir_limit.gif (at least those are the first ones I look at). While these will give you…
- 1 May 2012
Analog/Custom Design: What is Digitally Assisted Analog Design?

QiWang

Mixed-signal applications are among the fastest growing segments in the electronics and semiconductor industry. Applications in mobile communication, networking, power management, automotive, medical, imaging, safety and security require a very high integration of analog and digital functionality at system, SoC and IP levels.
Unfortunately, compared with the advancement of digital designs over the past decade, the state…
- 30 Apr 2012
System, PCB, & Package Design : What's Good About Allegro Via Patterns During Group Routing? See for Yourself in 16.5!

Jerry GenPart

New to the 16.5 release of Allegro PCB Editor is the ability to establish via patterns during group routing.
Group Routing Review
The Allegro PCB Editor supports interactive group routing. Interactive group routing is the routing of more than one net concurrently. You can use this feature when routing a bus with traces that follow the same path and have common physical and electrical rules. To specify the nets for group…
- 30 Apr 2012
Verification: My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!

teamspecman

The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation problem that you might face. The most obvious and common generation problem is a contradiction, but the Gen Debugger can handle various other problems, such as user errors, performance problems and unexpected generation results.
In this post, we will focus on one of the most extreme cases of unexpected generation: a constraint which is…
- 24 Apr 2012
System, PCB, & Package Design : What's Good About OrCAD Capture’s Find Result Report? Look to SPB16.5 and See!

Jerry GenPart

The OrCAD Capture 16.5 release now has a method to generate a report (in CSV or HTML format) for the results from the Find command.

Read on for more details…
After you execute the Find command on a design, you can generate a report (in CSV or HTML format) for the results from the Find command. If you run the Find command to search for different types of objects in a design, the search results will display in different…
- 23 Apr 2012
System, PCB, & Package Design : What's Good About ADW’s Generic Models? Check out the 16.5 Release and See!

Jerry GenPart

The 16.5 release of Allegro Design Workbench (ADW) provides support for generic models. As you’ve seen in prior releases, ADW supports the typical Cadence SPB front-to-back models – symbols, footprints, etc. Now, we offer generic model support so you can construct new custom models like PSpice, IBIS and other simulation models.

Read on for more details …

We’ll illustrate the highlights of constructing…
- 19 Apr 2012
Verification: Analyzing Error Reports When Specman Crashes

teamspecman

One of the most frustrating events while running a tool would be to experience a tool crash.
In Specman you would usually see something like:
*** Error: OS signal 11 (segmentation violation) received
       See the stack trace in ./specman.err
To debug:
---------
o Rerun the same test with the same seed in interpreted mode, after
   setting "break on error". Load also any previously compiled modules.
   ** One user module is…
- 17 Apr 2012
Verification: Video: “Drive For Innovation” Finds It At Every Turn

jvh3

With some notable exceptions, too often technology trade press reporting has been as dour as the general world news. However, to EETimes editor Brian Fuller, this negativity was at odds with the inspiring technological advances that were regularly crossing his assignments desk. In a nutshell, Brian's confusion over this dichotomy was the seed crystal behind the "Drive for Innovation" -- a partnership between Avnet Express…
- 16 Apr 2012
Verification: Modeling Large Memories in SystemC

jasona

Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded systems have a gigabyte or more of SDRAM. For example, one of the Xilinx Zynq boards, known as ZC702, has a Linux Device Tree source file defining the memory s...
- 13 Apr 2012
Verification: Lessons from CDNLive! India Best Paper -- Property Driven Simulation in IEV

TeamVerify

Recently the CDNLive! India 2011 best paper award winner, "Complex IP Verification Methodology Using Property Driven Simulation in IEV," was published in TechOnline India. This is great news for the verification community because the techniques the NVidia authors describe have broad applications beyond the challenging memory controller project that was the subject of the article. Specifically, this case study…
- 13 Apr 2012
Analog/Custom Design: CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification

AElzeftawi

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High-performance digital verification and high accuracy analog verification represented the foundation for traditional AMS verification…
- 9 Apr 2012
Digital Design: When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi-cut Via Insertion Flows

wally1

Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings to achieve routing success?
Fortunately, the application note on NanoRoute Recommended Options is available to help…
- 5 Apr 2012

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.