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For years now consumer electronics have driven (nay, saved) the EDA industry.  Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business.  While I couldn't personally attend CES this year, I had two trusted agents (specifically, Unified Communications (UC) expert David Danto of Dimension Data, and Joseph Hupcey Jr., video…

Some of you may remember the blog written several years ago "Shhhhh...SpectreRF Tutorials and AppNotes - One of Our Best Kept Secrets".

Well, the more things change...the more things stay the same!   The location of these tutorials and appNotes...

Another high density interconnect (HDI) technology that has gained popularity is inset vias. The 16.5 release has provided new commands added in Allegro PCB Router to support inset vias.

Via in Pad pattern has been very popular due to its clear advantage of offering lower parasitics as compared to other fan-out patterns like dog bone patterns. But, it may pose a challenge for the assembler to deal with the trapped air…

Continuing the series of introducing you to the people that create the tools you use every day, in this video I ask Bob Kurshan, Cadence Fellow and R&D leader of the Incisive Formal Verifier ("IFV") "Engines Team," about the challenges and/or tradeoffs in creating a formal engine, how to avoid gotchas in tricky problems like cache coherency verification, and how formal technology might evolve over the next…

The 16.5 Allegro PCB Editor release adds differential pair phase tuning as an alternative to using the mouse guided delay tune command, and also quality improvements for transitions at region boundaries.

I’m providing a quick summary this week of these enhancements.

Differential Pair phase tuning

Phase Tuning is an alternative to using the mouse guided delay tune command and offers the precision of finite length adjustment…

Happy New Year!

After many requests, I set aside some time and updated the Using the nport in Spectre and SpectreRF Simulations appNote for MMSIM 11.1.   You may download the appNote on Cadence Online Support.   More nport enhancements are planned, so stay...

In case you missed any of the 5 free webinars Team Verify presented in 2011, you're in luck: all of them have been recorded and posted for you to review at your leisure. Take your pick from the following - or pop a bucket of popcorn and a family sized bag of chips and watch them all at once!

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How to Completely Eliminate SoC Connectivity Bugs - Really!

http://www.cadence.com/cadence/events/Pages/event.aspx?eventid…

My last "real-world assertions" blog post seems to have tickled a bunch of people with my story about the racy narration at the historic Red Fort in Delhi. I've heard from several folks who have also seen the show and had a similar reaction. Just out of curiosity, I did a Web search and found a half-dozen or so other blogs and travelogues with comments similar to mine. Concluding my series, and in the spirit…

The introduction of Apps in the new Cadence OrCAD Capture Marketplace in the 16.5 release brings a new level of feature customization to the designer in a proven, successful, delivery model. But what does this “design by plug-in” or “app-based” model really mean for users?

Apps, short for applications, are additional software designed to perform specific tasks. There are a vast array of design flows…

Continuing the series that introduces you to the people that create the tools you use every day, in this video R&D lead for expert-level use cases in Incisive Formal Verifier (a/k/a "IFV") Pradeep Goyal talks about the common use cases for "pure" formal users. He also notes how expert-level formal techniques might evolve over the next 5 years -- both alone, and in combination with simulation technologies…

Allow me to interrupt the excellent "Meet R&D" series to share a small holiday present.   On the Functional Verification Shared Code Forum I've just posted a ZIP file with Sudoku solver code for Incisive Enterprise Verifier (IEV). The file is at /forums/T/21110.aspx

The Details:
First, we map a standard 9x9 Sudoku puzzle into a 9x9 Verilog number array with unknown (X) locations, and then apply 3 sets of…

Although many automatic layout generation tools are available to automate design creation, the layout modification/correction step (fixing design rule violations) is not automated very well.  Consequently, design modification including error correction typically needs to be done manually. A good solution to automate the layout modification/correction step can be provided by a layout optimization tool that optimizes the…

The acid test of any conference is how long the information and lessons learned linger in your mind after the keynotes, panels, and demos wrap up.  Like last year, the 2011 edition of ARM Techcon is passing the test of time.  Below are some of the highlights that have stuck with me and/or have been prompted by follow-on news since the event.

This year's ARM Techcon highlighted advances on many fronts -
semiconductor…

Your favorite verification engineer has been good all year.  Thousands of tests run. Nights and weekends of debug.  So how do reward her? Why, with UVM Training, of course!

Cadence experts have trained hundreds of engineers on OVM and UVM.  These trainers have deep knowledge in both the methodology and the Incisive simulators that run it.  They track the latest activities in the Accellera Systems Initiative standards committee…

The 16.5 AMS library has a range of new models that can be used in diverse applications such as power supply, regulation and monitoring, and signal isolation. The new models include the following:

•    MOSFET Drivers
•    Alkaline Battery
•    Supervisory IC
•    Optocouplers

In addition, PWM and vendor models have been integrated with PSpice.

Read on for more details …

MOSFET Drivers
Two new MOSFET drivers, ISL6614…

On day-three of the Cadence Signal and Power Integrity Three Day Event, the audience was served up a dose of Robert Hanson expertise on managing power delivery networks.  Robert covered topics such as developing a bypass system, RLC of a bypass capacitor, power delivery, and capacitor parameters.  Robert interacted with the attendees in such a way that both those with a background and those without a background in the topic…

On day-two of the Cadence Signal and Power Integrity Three Day Event, it was standing room only as 100+ attendees listened in as Robert Hanson explained high speed interface design challenges associated with DDR3 and PCI Express 3.0.  Robert took the mystery out of designing for timing compliance as well as how to meet bit error rate specifications on multi-gigabit interfaces.

Robert's material on multi-gigabit interfaces…