Community

Designers normally create nets or groups of nets to assign constraints. This leads to nets rules, net class rules, and net class to class rules. As the size of physical symbols (footprints) is reducing, the need for region specific rules is also increasing.

When all these constraints are applied, the amount of memory consumption by the Allegro PCB Router increases. In 16.5, proper use of Net class and Net-class to class…

To complement our support of DAC, CDNLive, and other large-scale events, where the program touches on holistic approaches to whole levels of design and verification realization, Team Verify is also proud to host the "Club Formal" event series.  Patterned after the popular "ClubT" series for Specman users and other Trailblazers, Club Formal is a deep dive exclusively focused on topics in formal analysis and assertion…

I was asked recently about how to easily collect coverage on the sequences generated by the verification environment.  Since this question has come up before, I thought I would take this opportunity to write a short blog on how to quickly and easily collect coverage on generated sequences. 

A comprehensive coverage plan contains coverage of the DUT output, internals, and also the stimuli created and sent by the verification…

How many times have you done this: you want to flip or rotate a cell in your design, so you select it and hit the Q key. The Attribute Editor form pops up, you choose the orientation you want in the Orientation drop-down box, then hit OK or Apply. I know I have done this countless times in my years of chip design.

What if I told you there was a faster, easier way? Well, there is - and it's hidden under the Right Mouse…

One of the key tenants of the EDA360 vision is the need for scalable, correct-by-construction IP creation and integration of design and verification IP.  Duolog is in the vanguard of creating automation to address this challenge, and in this video update Duolog's CTO Dave Murray notes new capabilities with both Cadence and ARM-centric flows, how IP-XACT has become an extensible platform, and how the UVM standard (and…

At DAC 2011 I had the opportunity to reconnect with Yunshan Zhu, the CEO of NextOp Software. After a quick update on their flagship product (BugScope 3.0), Yunshan shares his observations on how assertion synthesis can complement the Universal Verification methodology (UVM), plus he reveals specific application spaces where they have seen BugScope be particularly effective.

If the video fails to play, click here.

Note:…

A couple of blog posts ago, I talked about the worldwide functional verification seminar series that we've been delivering this year. This has been a successful endeavor by almost any metric, but since it's taken a lot of my team's time and energy I'm continuing to monitor every aspect to ensure continued results. Last week I had the good fortune of traveling to Europe for seminars at a hotel in Grenoble and at…

Specmaniacs and IES-XL users around the world know that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting eRM, OVM, and now the full production UVM.  At DAC 2011, AMIQ introduced a long awaited feature to DVT for Specmaniacs in particular: direct integration with the Specman debugger.  In this interview shot on the DAC 2011 show floor, AMIQ CEO Cristian…

At DAC 2011, both myself and fellow Team Verify member Tom Anderson felt a distinct increase in the level of interest in Formal and assertion-based verification (ref. my DAC report, and Tom's).  We weren't the only ones: at the Oski Technology booth (the same formal verification service provider I spoke to back at DVCon) their representatives always seemed to be busy with prospects. This snapshot taken on the traditionally…

With the Allegro PCB Editor SPB16.5 release we've enhanced the existing Allegro drafting dimensioning capabilities, so that when a dimension is created involving one or more design database objects the dimension will subsequently remain internally ‘associated’ with those objects as well. Subsequent editing operations such as the moving of an object can then appropriately and automatically update as required any dimensions…

Wireless, networking, storage, computing and FPGA applications have been moving aggressively to advanced process nodes to take advantage of lower power consumption, improved performance and area reduction. Today, most of these applications integrate a significant amount of analog/mixed signal (AMS) or RF together with digital circuits. Since AMS often occupies over 50% of the chip area, applying traditional, conservative…

In addition to the annotated image gallery (click here or on the image), below are some long form comments on particular aspects of this year's Design Automation Conference (DAC).

Cloud computing - the title of Richard Goering's report on this panel captured the discussion perfectly, "DAC Panel Says ‘Yes' to EDA in the Cloud -- But Differs on When".  Of course there are a variety of private and…

How many times while working in Encounter Digital Implementation system have you wanted to find the transition time on a certain pin? How did you go about finding it? Here are some ways I know that I've used:

• If I knew the pin was failing the max_transition constraint, hunt it down in the .tran violation report.
• Try to find the pin somewhere in my timing reports and look at the slew column.
• Use (gasp!) undocumented commands…

Getting a complex mixed-signal design assembled and completely analyzed for mask design is a huge challenge today. The IPs are complex and too many decisions need to be made to meet design budgets. All this is not possible with anything less than a fully automated, front-to-back mixed-signal design solution.

On top of mixed-signal complexity, battery operated wireless and hand-held mobile applications are extremely sensitive…

I was at the Design Automation Conference (DAC) last week showcasing our latest, greatest Incisive Enterprise Simulator (IES) performance features in the demo suites.  In my "off" time, I was in our DAC booth meeting customers and discussing our advanced verification solutions.  I ran into a long-time SystemVerilog user who had been using that language since the AVM methodology days years ago.  He mentioned to…

In my last blog, Virtuoso Analog Design Environment XL - Embrace the Productivity, I wrote about Virtuoso Analog Design Environment XL's multi-test bench environment and how design teams can make use of this feature to increase productivity and use hardware resources efficiently. In this blog, I will focus on advanced Virtuoso Analog Design Environment XL features like corners analysis and Monte Carlo analysis.

Corners…

In this interview, members of the Texas Instrument wireless group talk about the characterization effort initiated and completed last year between Cadence and IBM using TI RF designs as a pilot. The goal between the two teams was to optimize SpectreRF...

The Allegro 16.5 release was made available on May 17, 2011!

This release adds additional improvements and efficiencies to your design process.

New technologies in Allegro 16.5 include advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design featured and flexible team-design enablement to address global designer productivity.

Today, I’ll discuss the enhancements…

Last week was the 48^th Design Automation Conference (DAC), held in lovely San Diego. This was the 24^th DAC in a row I've attended, which sounds impressive although I have a number of colleagues who go back even further. This year's attendance was significantly higher than last year's by just about every metric, not surprisingly since the economy has picked up a bit and San Diego is more of a draw than Anaheim…

The 20nm roadmap.  TSMC reference flow 12.  The UVM 1.1 release. Verification IP for ARM ACE.  Assertion-driven simulation.  All of these important items were key EDA360 deliverables this DAC.  Yet there was one thing that I dare say was the most anticipated part of the whole conference: of course, I'm referring to "The Denali Party".  Indeed, the #1 FAQ since Cadence's landmark acquisition of Denali last year was…

In response to the OrCAD and Allegro 16.5 product release, and the growing demand for easy to use and affordable Signal Integrity solutions such as OrCAD PCB SI, TeamOrCAD, TeamAllegro and Signal Integrity expert Robert Hanson will join forces the week of June 20 in Chelmsford, MA.

Cadence has opened up their training facilities to Robert Hanson to teach his popular SI/PI/EMC training courses.  On June 20-24, engineers…