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Analog/Custom Design: SKILL for the Skilled: The Partial Predicate Problem

Team SKILL

The partial predicate problem describes the type of problem encountered when a function needs to usually return a computed value, but also may need to return a special value indicating that the computation failed. Specifically, the problem arises if the caller cannot distinguish this special value from a successfully calculated value. In this posting of SKILL for the Skilled, we look at several ways to attach this problem…
- 19 Jun 2013
Verification: Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification

Jack Erickson

I've written a lot about the benefits of moving hardware design and verification up in abstraction from RTL to SystemC with transaction-level models (TLM). We have seen many customers speed their overall design and verification turnaround by 2x. ...
- 18 Jun 2013
System, PCB, & Package Design : What's Good About Allegro PCB Editor Net Groups? See for Yourself in 16.6!

Jerry GenPart

Just a brief blog today about a new feature in Allegro PCB Editor.
A new net grouping mechanism has been added in Allegro PCB Editor 16.6 called ‘NET_GROUPS’. Essentially, the Net Group replaces the bus object.
A Net Group is a collection of net objects. Different types of net objects, such as nets, buses, differential pairs, and XNets can be added as members of a Net Group. A net object can be a member of…
- 17 Jun 2013
Analog/Custom Design: Virtuosity: 10 Things I Learned in May by Browsing Cadence Online Support

stacyw

May was a big month for new videos. It was also a month that saw the release of Virtuoso IC6.1.6, with lots of great new features and the rollout of new enhancements to the Cadence Online Support website.
Videos
1. DMS Basics Series
This is a great series of 10 videos covering various topics in mixed-signal verification, real number modeling, and mixed-signal connectivity. You'll also notice all 10 videos referenced together…
- 14 Jun 2013
System, PCB, & Package Design : What's Good About RF PCB and Agilent ADS Via Exchange? 16.6 Has Many New Enhancements!

Jerry GenPart

The 16.6 Allegro PCB Editor and the Agilent Advanced Design System (ADS) interface have several new enhancements with respect to padstacks and vias.I will cover the Allegro generic via padstack that exports to ADS, and also the enhancements for existing layout IFF interface (import and export) to support the generic via exchange.
Layer-to-layer via structures are almost always used in PCB designs. These common structures…
- 11 Jun 2013
Verification: DAC 2013 – System Design on Wednesday, June 5th

fschirrmeister

The DAC exhibition comes to a close today, and we have another day with great presentations related to the Cadence System Development Suite. If you want to follow along the flow of our core engines from virtual through RTL simulation, acceleration...
- 5 Jun 2013
Verification: DAC 2013 – System Design on Tuesday, June 4

fschirrmeister

We had a great day on system design yesterday, followed by great party at Austin City Limits with "Asleep At The Wheel" and the EDA band around Jim Hogan. Today shapes up to be just as great! We started early today at 8:00am with our ...
- 4 Jun 2013
Verification: Accelerating Time to Market with ARM Software Development Tools and the Cadence System Development Suite

jasona

In one of the Monday presentations at the Cadence DAC Theater, Ronan Synnott from ARM talked about how ARM Software Development Tools such as DS-5 interact with the Cadence System Development Suite. I thought it would be good to provide a more detail...
- 3 Jun 2013
Verification: How Can You Continue Learning About Advanced Verification at Your Desk?

umery

How much time do you spend "playing" and "learning" before you try a new EDA tool, feature, or flow?
Do you really take a training class and sift through the documentation or books about the subject before you start project work? Or are you the type who has the knack of figuring things out on your own by taking a deep dive, head first?
Learning is an iterative and repetitive process. Human beings spend…
- 3 Jun 2013
Verification: DAC 2013 – System Design on Monday, June 3rd

fschirrmeister

The first day of DAC starts off today with four great presentations on system design at our DAC Theatre. Freescale will present on their use of FPGA-based prototyping, AMD will show their enhanced use of Palladium together with TLM models, ARM wil...
- 3 Jun 2013
Verification: Welcome to DAC 2013!

jasona

I just arrived at DAC 2013 in Austin, and as always I'll be writing about the interactions of software and hardware. This is the 50th DAC, and about 20 years of DAC for me. Although I have not been to every DAC over this ...
- 2 Jun 2013
Verification: Introducing UVM Multi-Language Open Architecture

Adam Sherer

The new UVM Multi-Language (ML) Open Architecture (OA) posted to the new UVMWorld is the result of a collaboration between Cadence and AMD. It uniquely integrates e, SystemVerilog, SystemC, C/C+, and other languages into a cohesive verification hierarchy and runs on multiple simulators. Moreover, the new solution is open for additional collaboration and technology enhancement.
Since Cadence introduced ML verification four…
- 31 May 2013
System, PCB, & Package Design : Customer Support Recommended - Flex PCB Design Features in Allegro PCB Editor

Naveen

Flexible PCBs are used widely in everyday technology and electronics in addition to high-end, complex completed components. Two of the most prominent examples of flexible circuit usage are in hard disk drives and desktop printers. The following blog highlights the features of Allegro PCB Editor (Allegro) along with the Miniaturization option that provides a routing solution for flexible (flex) circuits.
Flexible Circuit…
- 31 May 2013
Analog/Custom Design: Mixed-Signal -- Successful Tech-on-Tours, Huge Focus at DAC 2013

Sathish Bala

We just completed some hugely successful Mixed-Signal Tech-on-Tours in North America. I am back in San Jose after this whirlwind trip that covered 9 cities in 4 weeks. Even though being on the road does get tedious, what kept me excited was the enthusiasm shown among Cadence customers for the Mixed-Signal Tech-on-Tour events. Close to 400 customers attended these Mixed-Signal Tech-On-Tour events.

The Dallas Mixed-Signal…
- 31 May 2013
System, PCB, & Package Design : What's Good About PCB SI AutoSolving Models in SigXplorer? You’ll Need the 16.6 Release to See!

Jerry GenPart

In previous releases, when you extract a net into SigXplorer, all the structures are automatically solved in Allegro PCB SI and then passed to SigXplorer. At times, the layerstack of the extracted structure might differ from the real layerstack in terms of the voids in a plane layer or shapes on the conducting layer. In such cases, the structure needs to be re-solved in SigXplorer. At other times, a field solution in…
- 29 May 2013
Verification: DAC 2013 – Software Driven EDA for the “Age of Gods”

fschirrmeister

This year's Design Automation Conference is less than a week away, and it's time for my preview of what to see at DAC. Last year I had likened my passion for system-level design to the Energizer Bunny, keeping on drumming. Maybe that year was...
- 28 May 2013
Verification: Why are Cadence and Forte Presenting Together at DAC?

Jack Erickson

You may or may not have noticed that Cadence's DAC Theater schedule features an intriguing combination of presenters next Tuesday:Tuesday, June 04, 2013 TimeCompanyTopic.........11:30 AMForte and CadenceHow to Broadly Deploy System...
- 28 May 2013
Verification: New Specman Coverage Engine - Extensions Under Subtypes

teamspecman

This is first in a series of three blog posts that are going to present some powerful enhancements that were added to Specman 12.2 in order to ease the modeling of a multi-instance coverage environment. In this blog we're going to focus on the first enhancement, while the other two enhancements will be described in the following coverage blogs.
Starting with Specman 12.2, one can define the coverage options per subtype…
- 28 May 2013
RF Engineering: SpectreRF at 2013 IEEE/MTT-S International Microwave Symposium in Seattle, Washington

Tawna
If you are attending the International Microwave Symposium (IMS 2013) in Seattle (June 2-7, 2013) stop by the Cadence Design Systems booth, #427.

We will be showing new MMSIM12.1.1 features including

“Smart” HB GUI,

Robust and easy to...
- 23 May 2013
Analog/Custom Design: SKILL for the Skilled: Part 9, Many Ways to Sum a List

Team SKILL

In the previous postings of SKILL for the Skilled, we've looked at different ways to sum the elements of a list of numbers. In this posting, we'll look at at least one way to NOT sum a list.
In my most recent posting, the particular subject was how to use SKILL++ to define a make_adder function. I commented in that article that the same thing would not work in traditional SKILL. In this posting, I'd like to walk…
- 22 May 2013
System, PCB, & Package Design : Help Shape Future Releases of APD and SiP – Provide Your Feedback on Early Adopter Features!

Jeff Gallagher

With every new release of the Cadence IC Package design software, many new features requested by designers are added. In other cases, interesting concepts that R&D engineers think up also make it into this list, so that real designers can try the...
- 20 May 2013
System, PCB, & Package Design : What's Good About Allegro PCB Editor Quickplace Overlap? Check Out 16.6!

Jerry GenPart

Just a very "quick read" on a new option for Quickplace this week.
The Allegro PCB Editor Quickplace is an application used to ‘quickly’ scatter components around the perimeter of the design or to a room location. By default, components are placed not to overlap each other. As a result, the application may fail to place components if space is not available. A new control option in the 16.6 release,"Overlap components…
- 20 May 2013
Verification: The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis?

Jack Erickson

The electronics industry has enjoyed constant growth while undergoing constant transformation. One of the most significant transformations has been the source of that growth -- from the PC revolution, to the rise of the internet, to mobile computing....
- 14 May 2013
Analog/Custom Design: Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support

stacyw

I'll confess: I didn't learn all of this strictly by browsing https://support.cadence.com/ (Cadence Online Support). I also wandered over onto /blogs/ii (Industry Insights blog) and http://www.cadence.com/cadence/events (Cadence Events), which were well worth a look.
Application Note
1. Demystifying NCELAB
You've gotta love any technical document that begins with the word "demystifying". Explains typical…
- 13 May 2013
System, PCB, & Package Design : What's Good About AMS Data Precision Options? They’re in the 16.6 Release!

Jerry GenPart

Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed on a large voltage, the resulting voltage loses its resolution, displaying staircase waveforms. With 64-bit precision, for the same signal, a perfect ramp waveform is displayed…
- 13 May 2013

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