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I recently came across a Wall Street Journal article,"ARM Chases Bigger Slice of Smaller Chips,"  that provides a very interesting perspective on how ARM is positioned to capture the microcontroller market, which is its next growth area. ARM based microprocessors are clearly dominating the mobile products from smart phones to tablets across Windows, Android and IOS mobile eco-systems. Most of these devices are…

Starting with release 16.5, it is possible to export data from Allegro PCB Editor into PDF files. PDF files are more portable and secure in comparison to .brd files and can be used by customers to share a subset of design data with their vendors who do not need direct access to design data. PDF files can easily be posted on websites and opened within browsers.

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Basic Information

The PDF…

Please join Team Verify and other design and verification engineers at the next "Club Formal" on the Cadence San Jose campus on Wednesday, October 17 at 11:30am. This free, half-day event (including lunch) is a great opportunity to learn more about general advances in formal analysis and assertion-based verification, and to network with others in your field.  Based on attendee feedback from previous events, we…

Recall the sumlist_1a function

In a previous posting the function sumlist_1a was defined.

(defun sumlist_1a (numbers)
  (let ((sum 0))
    (foreach number numbers
      sum = sum + number)
    sum))

Describing this algorithm in…

Right up there with functional verification, the challenges of low power design and verification present an existential threat to our customers' products, and ultimately their businesses.  Clearly both sides of the low power coin -- reducing generated heat and/or increasing efficiency to make the most of every available joule -- are of primary concern.  But what happens when external, environmental factors conspire…

The 16.5 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide a more flexible and robust designer experience. It can now be launched in a stand-alone mode, is faster in launching, can open multiple flows, and you can customize it by adding new buttons!

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Here’s a screenshot of the new Flow Manager:

You can open the last project, and select from a list of last used…

(defun sumlist_1b (numbers)
  (apply plus numbers))

In this posting, (Part 2), we'll look at improving this implementation by using the apply function with more than two arguments to enable handling…

You've placed and routed your design in the Encounter Digital Implementation (EDI) System. It passed Verify Geometry and Verify Connectivity without a violation. Great!

But when you run DRC signoff with your physical verification tool, you have violations related to the routing. What should you do now?

Depending on your situation there are usually two solutions:

1. Fix the violations by hand. This is okay if there are…

Apologies for the long delay between articles (best intentions and all that).  I last left you with an article about how to parameterize and manipulate device properties in your design without having to edit the schematic.  A very handy feature.  So there you are -- creating and matching and ratioing parameters willy-nilly.  You've changed values and defined ranges and run sweeps. 

And now you're wondering--how in the…

I want to show a few of these examples in this blog post (and a few upcoming posts…

In this post, we will discuss the interesting challenge of reset during simulation.

Specman has a very robust implementation of reset during test, which imitates a return to cycle 0. All threads are terminated, the run() method is called again, and evaluation of temporal expressions is restarted. UVM Testflow has the option to go back to any phase, not just to cycle 0, by calling rerun_phase(target phase). When issuing…

So you are developing your verification environment in e, and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate from e to UVM e?"

Well, this is a bit of a trick question. The short answer is that if you've adopted eRM in the…

The current Allegro Design Entry HDL (DEHDL) Page Search toolbar works only on the currently opened schematic page. If the scope of the search is different from the current page, then the Advanced Find & Navigate functionality can be used. This new feature also allows you to define the objects which you would like to search for the text.

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The Find Filter (available from the Page Search…

The 16.5 PCB SI product’s rectangular mesh scheme is used for shapes, cutouts, slots, anti-pads and voids within shapes. The mesh cell size you pre-specify is the maximum cell size ,and the system will automatically adjust/reduce the cell size if necessary. You can ignore the meshing for anti-pads and small shapes/voids through the Preferences settings.

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Analyze Menu

All analysis…

Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this year. However, there was one presentation titled "Metric Driven Verification Approach for Analog/Mixed Signal IPs" authored…

The use of separate force (F) and sense (S) connections (often referred to as a Kelvin connection) is a common requirement in the PCB design. The separate force (F) and sense (S) connection at the load eliminates any errors resulting from voltage drops in the force lead. The Kelvin Sense connection is routed by separating the sensing signals (S) from the lines, and delivering the power to the load (F). This type of connection…

The 16.5 Allegro Package Design (APD) product has been modified to provide a different type of method to control wire bond settings for groups. It is important to note the differences between these new group settings and the wire bond groups that existed prior to 16.5. In these prior releases, a wire bond had to strictly adhere to a wire bond group, whereby the group defined the characteristics of the wire bond. In contrast…

Luckily I was able to track down my very busy colleague Bin Ju between assignments and interview her about her first-hand observations of what's going on here in Silicon Valley today.  Bin is an expert on formal and assertion-based verification (ABV), so her remarks focus on the trend toward increasing adoption of formal analysis, how users are leveraging "formal apps" to enable rapid adoption of this technology by…

Last week, a favorite customer of mine called me in a panic, just days from tape-out of a large multimedia SoC. After a minor change in their RTL code their Specman testbench started crashing, even though the e code wasn't changed. Could I help?

Knowing that this customer compiles their e code, and that Specman doesn't tend to crash, the first thing I did was to get them to recompile the e code with the debug…

The 16.5 Allegro PCB Router has a couple new improvements I’ll cover today – Embedded Components Support and Route Quality Improvements.

Read on for more details …


Embedded Components Support

This functionality is basically transparent to the Allegro flow designer. The Router will just translate and route these components normally. For standalone users of the Allegro PCB Router, a new syntax has been added…