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The 16.5 Allegro PCB Editor release contains several updates to the Graphical User Interface (GUI) to increase your efficiency and productivity in using the product.

Read on for more details...

Status Bar updates

Functional responses can be obtained by clicking fields in the status bar. For example, the field indicating the current subclass can be selected and changed to a new class/subclass. This is a good alternative…

It is not often that an IP provider gets to showcase their IP performance in a real product demo. Those laurels usually end up going to the end product that uses the IP. But a recent Cadence video features our PCI Express (PCIe) Gen 3 core running flawlessly in silicon in a real system.

We thought we would raise some eyebrows since, as of today, there are very few products in the market that utilize the full power of…

Starting from version 12.1, the SimVision Watch Window accommodates Specman watch items together with HDL watch items. Now you can use the same window to inspect all your watches.

Hyperlink support in the SimVision Watch Window is still on its way, so right now Specview is the default for Specman watches. Nevertheless, you are invited to try out the new feature and voice your opinion.

To choose which watch window should…

I mentioned in my first blog one of my roles in customer support is to identify and author knowledge content for Cadence Online Support (https://support.cadence.com/). In this blog post I want to highlight some of the popular Encounter Design Implementation (EDI) System content published in recent months.

If you're not receiving email notifications on the latest Cadence Online Support content, log in to https://support…

Okay, this one is too cool not to share.

The other day a customer and I were trying to understand a tool behavior better so we did what we all do in desperate times: We read the documentation.

As straightforward as "reading the documentation" would seem, I bet no two users of the system interact with documentation the same way. Some people like to bring up "cdnshelp" at the UNIX prompt. Some like to download…

Over the past several years at various EDA trade events, one of the more popular forums have been panel discussions and interviews asking teenagers about the technology in their daily lives.  However, those forums have been comprised of amateurs, whereas in this interview I've secured a professional technology consultant -- Ms. Kristine Bonhoff, a college student by day, and a paid technical coach and volunteer in her…

Verifiers rejoice: R&D has just released all-new Assertion-Based Verification IP (ABVIP) code as part of Cadence's Verification IP (VIP) and SoC Catalog offerings.  Specifically, the ABVIP code in the July 2012 release has been completely re-architected to be: 

• Higher performing for both Incisive formal and simulation engines (with gains from 1.5x to ~ 10x!)
• Simpler to instantiate and configure
• Easier to use with…

In looking over the shoulders of Encounter users over the years I've found there's a bunch of little tips and tricks I use to make interacting with the tool a little easier that aren't necessarily immediately obvious. Here are some of the more common ones I used this week:

1. When navigating an Encounter log file in a text editor, search forward for "<CMD>". Each time a command is executed it's embedded…

E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through my DVCon 2012 folder -- lo and behold I came across the following video interview.  It was shot during the show, but the official approval fell between the cracks and didn't come through until recently.   Regardless, the issues raised in the paper that's the subject of the interview (From Spec to Verification Closure: A Case Study…

Incorrectly written constraints can negatively impact aspects such as generation order or input sampling, leading to incorrect or problematic generation.…

In my last post I wrote about writing more compact db access scripts with dbGet's expression-based matching. We found all of the high fanout nets in the design which weren't clock nets:

dbGet [dbGet top.nets {.numInputTerms > 16 && .isClock == 0}].name

This writes the name of each net to the console. But how would we write those nets to a file? Say, for example, if we wanted to call optDesign -selected…

Our Silicon Package Board (SPB) Customer Support team has initiated a new blog series promoting specific Application Notes (AppNotes) that we believe will help our customers increase their productivity in using our solutions, flows, and products.

Our Customer Support team will review new and existing Cadence Online Support published AppNotes on a periodic basis and select the “Best of the Best” for those we believe will…

While working on very large scale Printed Circuit Board (PCB) files that contain a huge stack-up along with thousands of footprints and numerous shapes, the performance of the  Allegro PCB Editor plays an important role in getting the board built in time. Below are example statistics for a large scale PCB:

Apart from upgrading the platform hardware to have more RAM, multi-core processor, or a better graphics adapter, there…

• 1. What domains are in the environment? What units do they contain?
• 2. What phase is running now?
• 3. Why are we still in this phase? Which activity is still running, and blocking us from…

As you know, Cadence Online Support is your 24/7 site for getting help and resolving issues related to Cadence software. If you are signed up for e-mail notifications, you've noticed new solutions, application notes, videos and other content are added daily. In this blog I want to highlight a new content type called the Rapid Adoption Kit (RAK). This new content type is a packaging of related material to demonstrate how…

Until recently, Specman used to look for its licenses in the following strict, hardcoded order:

Either

1. "Incisive Specman Elite"

2. "Incisive Enterprise Simulator"

3. "Incisive Enterprise Verifier"

1. "Incisive Enterprise Simulator"

2. "Incisive Enterprise Verifier"

3. "Incisive Specman Elite"

Starting from Specman 12.1, Specman supports -uselicense and -noie…

This week, I'm providing a very short blog. While the content is brief and simple, the positive impact to the Allegro Design Entry CIS usability is high!

The Capture INI (project level) settings are always dynamic, the CIS settings are more or less static and usually do not change after the initial CIS database related setup. You may often need to clear out and reinitialize your Capture INI settings, but may still…

Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University of Bristol, UK, teaches a course on functional verification.  In this interview she outlines how the course is structured, what makes for a good verification engineer, and anecdotes of how students are getting snapped up by industry immediately upon graduation. 

If the embedded video doesn't play, click here.

Brief digression in…

Readers of this blog and of Team Specman will recall that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting functional verification methodologies and testbench creation for years.  The success of verification engineers using AMIQ's "DVT" IDE product has been increasingly noticed by their RTL designer colleagues such that AMIQ is now adding new capabilities…