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Mechanical part support! It's here in the Allegro Design Workbench (ADW16.3) release! 

There are new data model types in ADW16.3 that provide a solution for the support of mechanical models in the library and design flow. The mechanical model types supported in this release include three basic model categories – Allegro PCB Editor, Design Entry HDL (DEHDL), and Mechanical Kits.

Allegro PCB Editor mechanical models…

MDL is an immensely powerful feature in our simulators that allows designers to run better simulations quicker.  Below is a quick demo to get you started -- and be sure to try out the workshop in your hierarchy under <MMSIM_installation>/tools/spectre/examples/MDL_workshop.

If video fails to play click here.

Below are some solid SpectreMDL examples and tips from our Support knowledgebase that show what else it…

Measurement Description Language (MDL) is an immensely powerful feature in our simulators that is frequently overlooked.  MDL gives the designer advanced control of our simulators allowing them to run better simulations quicker.  Below is a quick demo to get you started. Also, be sure to try out the workshop in your hierarchy under <MMSIM_installation>/tools/spectre/examples/MDL_workshop.

If video fails to…

PCB Librarian Expert (sometimes known as Part Developer or PDV) is the librarian tool used for generating all the parts that are used in Allegro Design Entry HDL (DEHDL) and Allegro System Architect (ASA) based designs. These parts contain symbols which are placed on the schematic canvas and connected to capture the design logic. In the SPB16.3 release, with the availability of font support in DEHDL, this same font support…

I've just returned from CDNLive! India in Bangalore, fired up with the huge crowd, their avid interest in Cadence and our products, and both the quantity and the quality of the user sessions. Of course I was impressed with CDNLive! here in Silicon Valley too; I blogged about that a couple of weeks ago. But the India show has at least as many attendees, plus there was something extra in their level of enthusiasm…

This is second in a series of blog posts about making your design cycles shorter and more predictable for increasingly complex PCB designs. In my last post I talked about using ECSets and Topology Apply capabilities for high-speed standards based interfaces such as DDRx and PCI Express.

Continuing on that theme, implementing high-speed signals can be a challenge as the delay tolerances shrink and matching requirements…

The SPB16.3 PCB SI release has simplified the use of case management.

In previous releases, a Signoise case management dialog often appeared after changing SI parameters or before running a simulation. This dialog is shown below:

 
The purpose of this dialog was to allow you to control what to do with existing simulation data that might now be out of date. The options provided by this dialog are:

• Save the existing simulation…

Shortly after DAC 2010, Gabe Morretti wrote a couple of interesting blogs (reference links below) on how associating the name "verification" with formal was a bit of a misnomer.  (Just to be clear, Gabe was referring to formal property verification (FPV) and not formal equivalence verification.)  He feels the label should be "Formal Design" and justifies this by the fact that assertions need to be developed simultaneously…

Traditionally, envelope analysis is used to simulate circuits with modulated inputs. 

Envelope analysis is much faster than transient simulation, and is used for simulating spectral regrowth.  

Regular envelope analysis is "brute force" transistor-level...

This new SPB16.3 Global Route Environment (GRE) Plan Status and Router Status functionality will assist you in finding errors and is designed to make it easier to work with the router and obtain feedback from the router. It employs a Constraint Manager type spreadsheet interface with cells that are active. In other words, you can execute commands on the data found within the cells.

The Plan Status and Router Status forms…

If you are running short on time and can't view all the videos of the 2010 CDNLive Silicon Valley in San Jose, CA on October 26 posted here: www.cadence.com/cdnlive/na/2010/pages/default.aspx  consider this photo blog as your very own "Cliff Notes" version. Click here to go to the gallery.

* The main stage keynote presentations and panel discussion

* Verification…

Although I attend a number of conferences and tradeshows each year, most of these are rather EDA-centric. But last week I was in Irvine for the eighth annual International System-on-Chip (SoC) Conference. It is a fairly small event -- more like a workshop in some ways -- with a single track over its two days. I do not believe that I have ever been to any conference with such a diverse range of topics in one track…

The SKILL programming language augments Cadence core tool functionality for Virtuoso and Allegro customers. It is also an important development tool for internal Cadence services organizations as well as Cadence product development groups. We see the value, power, flexibility, and elegance of the language as an enabling tool for customizing and enhancing design environments. These capabilities are made possible…

I previously wrote about the general session of the 2010 CDNLive! Silicon Valley conference, focusing on what EDA360 means for Digital Implementation engineers.  Today I wanted to share a little more about a couple of papers I co-presented along with Cadence customers.  I enjoy co-presenting with customers where I, as a Cadence Applications Engineer, describe a piece of functionality in the system and then a customer…

There are a couple new Differential Pair (Diff Pair) capabilities available with the SPB16.3 Allegro PCB Editor Constraint Manager - Differential Pair Renaming and Dynamic Phase Control for Differential Pairs.

Differential Pair Renaming

Prior to the SPB16.3 release, library and model-defined differential pairs are automatically named based upon the member nets of the differential pair. However, you might want to rename…

With all due respect to our Tech Pubs writers, Solutions Architects, and contributors to this blog, nothing beats hearing the experiences of end users applying a given tool or methodology to their real world challenges.  Fortunately, Team Verify has been blessed with a generous and prolific community of users who have taken the time to share their experiences in pure formal verification, multi-engine mixes of formal and…

Well, we all survived another very busy CDNLive! event last week. Since I posted a preview beforehand I would be remiss if I didn't let you know what happened. The bottom line is that this was a really good show, with more than forty talks covering a wide range of EDA and EDA360 topics. The majority of these were presented by customers, with some additional sessions from Cadence management and technical experts…