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Latest Blog Posts

  • Verification: Specman/IES-XL 9.2 Is Posted - Come And Get It!

    teamspecman
    teamspecman

    We interrupt the Specman 9.2 preview series and ClubT news to announce that 9.2 is now posted on downloads.cadence.com, under the "INCISIV92" umbrella!

    Hence, for those of you who couldn't get to a recent ClubT, CDNLive, or Incisive Seminar, our "9.2 preview series" is changing into the "9.2 highlights series", covering the major new features announced back at DAC.

    Happy Verifying!

    Team…

    • 22 Oct 2009
  • Verification: Why OVM? John Aynsley of Doulos Has 10 Reasons

    Adam Sherer
    Adam Sherer

    Believe it or not, sometimes a marketing guy just needs to say less. It's true. It does happen. Sometimes we do just get right to the point. Yeah, we do blather on sometimes but ... oops, there I go again. Just listen to John. He has 10 great reasons to adopt the OVM.


    If video fails to play please click here.


    Question? You can post them here or send them directly to John at john.aynsley@doulos.c…

    • 22 Oct 2009
  • System, PCB, & Package Design : What's Good About Package Power Integrity? You'll Need SPB16.2 To See!

    Jerry GenPart
    Jerry GenPart

    As clock and data frequencies increase and high-speed systems become ever more densely populated, the distribution of power becomes a major challenge for package power/ground design. To ensure that high-speed systems continue to deliver the required performance at these new signal frequencies, power distribution impedance has to be controlled over a wider range of frequencies. This can be accomplished through careful…

    • 21 Oct 2009
  • Verification: Demo: New Signal Tracing Capability in Incisive Enterprise Simulator

    archive
    archive

    One of the great things about working here at Cadence is having the opportunity to test and preview new features and functionality before public release.  The newly released 9.2 version of Incisive Enterprise Simulator contains a new streamlined signal tracing function in SimVision.

    I thought you might like to see a preview demonstrating the new capabilities for tracing signals directly within the source browser, as well as updates…

    • 21 Oct 2009
  • Verification: Extending Multiple When-Subtypes Simultaneously

    teamspecman
    teamspecman

    [For those of you that didn't / can't make it to a ClubT last week/this week, here is a meaty technical article from guest bloggers Matan Vax (R&D Architect), Yuri Tsoglin (R&D), and Dean D'Mello (CoreComp Architect)]

    When subtypes let you add properties and behavior to a struct or a unit when one or more enumerated/boolean fields take on specific values. The fields that define when subtypes…

    • 20 Oct 2009
  • Verification: Synopsys’ “Synphony” Announcement – Welcome to the Party!

    archive
    archive
    I’m glad Synopsys realized the world really IS moving to the next higher level of abstraction above RTL and now the party can really get started! It’s great for RTL designers, for their companies, and the EDA industry. With the huge produ...
    • 14 Oct 2009
  • Verification: Incisive Enterprise Verifier for Everyone!

    tomacadence
    tomacadence

    Last week Cadence announced a new product called Incisive Enterprise Verifier (IEV) that combines simulation and formal technologies in unique and interesting ways. I am very excited about IEV for two good reasons. The first is simply that it's the product I've been most involved with during my time at Cadence, so I have a personal stake in its success. The bigger reason is my vision that IEV will be the primary tool…

    • 14 Oct 2009
  • Verification: The Scoop on the New Incisive Enterprise Verifier

    Sarah Lynne
    Sarah Lynne

    Last week we announced Incisive Enterprise Verifier (IEV). What is cool about IEV is that it integrates formal analysis and simulation engines in unique ways that provide users with more power. One of the great things about IEV is that it is easy to use and get value quickly. It is all about helping to reduce the overall verification time.

    Take a look at the press release, and read Richard Goering's blog …

    • 13 Oct 2009
  • Verification: Webcast: EDA, ESL and More Ideas From DAC

    jasona
    jasona
    From the events calendar, OpenSystems Media is hosting a webcast tomorrow titled EDA, ESL, and More Ideas from DAC that will be hosted by Don Dingee and feature presentations and discussion from Frank Schirrmeister from Synopsys, Shabtay Matalon...
    • 13 Oct 2009
  • Verification: Virtualization and Simulation Roundtable

    jasona
    jasona
    A couple of weeks ago I participated in a roundtable discussion led by Peggy Aycinena that has been summarized and posted on edacafe.com. Please have a look if you are interested in Virtual Platform usage for embedded software.One of the things ...
    • 13 Oct 2009
  • Verification: Spanning the Globe to Bring You the Constant Variety of Verification

    jvh3
    jvh3

    Any sports fan living in the US during the 70's and 80's will remember the dramatic introduction to ABC television's "Wide World of Sports":

    "Spanning the globe to bring you the constant variety of sport… the thrill of victory… and the agony of defeat… the human drama of athletic competition… This is ABC's Wide World of Sports!"

    I'll leave it…

    • 12 Oct 2009
  • Verification: UPDATE: EU ClubT's Start This Week!

    teamspecman
    teamspecman

    Just a quick reminder that the ClubT series starts this week! Here are the specific dates and locations:

    • Feldkirchen (Munich area), Germany on this Thursday October 15
    • Eindhoven, The Netherlands on this Friday October 16
    • Grenoble, France this coming Monday October 19
    • Bristol, UK next Wednesday October 21

    As always, these free events feature direct contact with Cadence R&D and Methodology experts to share developments…

    • 12 Oct 2009
  • Digital Design: Leakage Power and National Security

    Rich Owen
    Rich Owen

    I read an interesting article recently on EDN regarding a new way to determine cryptographic keys using leakage power. Differential power has long been documented to be a method of cracking keys. In this paper, the author, Milena Jovanovic of the University of Montenegro demonstrated that leakage power can also be used to predict the key contents.

    I can’t pretend to understand the techniques behind cryptography…

    • 9 Oct 2009
  • System, PCB, & Package Design : What's Good About PDV Symbol Property Templates? The Secret's in the SPB16.2 Release!

    Jerry GenPart
    Jerry GenPart

    Allegro PCB Librarian / Part Developer (PDV) Symbol Property Templates have been a very beneficial feature in the SPB16.2 release.

    IEEE standards define a certain set of properties and their attributes for a symbol. Adding these properties individually to each symbol and setting the attributes according to the defined standards is a time-consuming and error-prone task for librarians. The Part Developer SPB16.2 release…

    • 7 Oct 2009
  • Digital Design: Running Low on Power or Receiving Mixed Signals? Talk to the Expert Users

    archive
    archive

    Everytime my wife and I are looking to buy a big item, we do our research by reading blogs, articles, and customer reviews. I have to tell you, the single best source for information is through customer reviews and testimonials by actual users. Testimonials not only included the good stuff, but they also include items that cover 'areas of improvement' in a particular product.

    I think the concept is applicable…

    • 6 Oct 2009
  • Verification: Intrusive Software Debugging: Friend or Foe?

    jasona
    jasona
    One of the great benefits of working with simulation (RTL, SystemC, or any Virtual Platform) is the ability to provide non-intrusive interactive software debugging. Interactive software debugging provides the control and data access needed to in...
    • 6 Oct 2009
  • Verification: Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!

    archive
    archive
    Last week Cadence’s new CMO John Bruggeman extended a personal invitation to all of you to join us for CDNLive San Jose 2009.   With 60+ papers, tutorials, and workshops, live and webcasted, we’re expecting even bigger attend...
    • 3 Oct 2009
  • System, PCB, & Package Design : What's Good About APD's Design Integrity Check? - It's in SPB16.2!

    Jerry GenPart
    Jerry GenPart

    The Cadence IC Packaging tools are complex, flexible tools that allow a designer freedom to create a package substrate layout in a myriad of ways. As a result, it becomes possible to run a particular feature at a time when the database is ill-configured to handle the request. Or, a given command could have a bug which results in the corruption of a specific database object in a manner that is not illegal to the database…

    • 30 Sep 2009
  • Verification: The Power of Parallel Thinking: Multi-Core Cadence

    tomacadence
    tomacadence

    A while back, as we were preparing to launch our first phase of multi-core support in the Cadence Incisive Enterprise Simulator family, we started working on a press release. We decided to include the multi-core support added recently to Incisive Formal Verifier, in which formal engines can run in parallel to deliver assertion results faster. Then Yoon Kim, my neighbor in the next office, mentioned that Conformal Equivalence…

    • 30 Sep 2009
  • Verification: Using Vera is like Speaking Sumerian – Who’s Left to Understand?

    Adam Sherer
    Adam Sherer

    Just like natural languages, non-standard verification languages can fade away.  Sure, ancient Sumerian exists in the Code of Hammurabi, but all modern law is written in living languages.  Similarly, verification environments and VIP still exist in Vera, but a shrinking population understands and uses it.  To preserve the investment, that code base need to be both translated into a standard language like SystemVerilog…

    • 30 Sep 2009
  • Verification: Verification is a Sprint and a Marathon!

    Adam Sherer
    Adam Sherer

    Verification engineers have updated an old adage to discribe their projects:  Verification is both a sprint and a marathon!  We need to optimize everything from single simulation runs to the complete suite of regression tests and every task in between.  Cadence answered that comprehensive call in the Performance Leadership announcement issued September 29th, 2009.

    This intrepid blogger thrives in the land of performance and…

    • 30 Sep 2009
  • Verification: CDNLive San Jose 2009 for the Specmaniac

    teamspecman
    teamspecman

    Even sooner than the EU ClubTs is CDNLive San Jose 2009, where this year the event is a "hybrid" format of in-person workshops and on-line webinars.  As with past CDNLive's, the agenda spans the entire Cadence product line, subdivided into tracks for the major segments of the design & verification flow.  Of course, Functional Verification and System Design & Verification are major tracks:

    http://www…

    • 30 Sep 2009
  • Verification: EU Specmaniacs: ClubTs Are Coming in 2 Weeks!

    teamspecman
    teamspecman

    EU-based Specmaniacs and "Trailblazers" rejoice: the annual ClubT series is back!  As always, these free events feature direct contact with Cadence R&D and Methodology experts to share developments in advanced verification, updates to the "Trailblazer" program, and hear your emerging challenges and concerns.

    In fact, we welcome YOU to present at ClubT!  If you have a 30-40 minute presentation on verification…

    • 29 Sep 2009
  • Verification: Must Have Advanced Verification to Achieve Software Signoff

    Steve Brown
    Steve Brown
    In a recent blog on EDA Graffiti,  Paul McClellan he talks about Software Signoff. He loosely defines it as high level synthesis of C/C++ describing the system, with some of the code built into an FPGA and the rest remains application software. ...
    • 24 Sep 2009
  • Verification: Specman 9.2 Preview: A Fresh Profile on the Profiler

    teamspecman
    teamspecman

    [Preface: all features in the 9.2 preview series are in Beta now.  We invite you to sign-up for the beta program and give this feature a test drive!]
    [Team Specman welcomes Avi Bloch from Specman R&D to introduce one of “his” new features.]

    Abstract
    Starting in Specman/IES-XL 9.2, users will be able to split the profiling process into separate run and analysis phases. This allows users to generate a profiler…

    • 23 Sep 2009
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