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I've been having a lot of fun with power switch cells lately. That's a whole other story (and perhaps a future blog entry), but in my experiments I was able to use dbGet in some neat ways. I posted previously about getting started with dbGet here.

After you've experimented with dbGet for a while, the natural next step is to start using it in scripts or pieces of code.

The scenario: All of my switch cells were…

Cadence will present SpectreRF Noise aware PLL flow latest enhancements at the DesignCon 2009 conference, based in Santa Clara . In the paper "Noise and Jitter Analysis for PLL-Based Frequency Synthesizer", we fully describe SpectreRF flow and provide...

It's here! It's really here!!!

I've spoken with many customers over the past several years and so many have requested an automatic Table of Contents (TOC) generator for Allegro Design Entry HDL (DEHDL).

In most of the designs you construct, the first sheet (or sheets) of the schematic design contain a table of contents (TOC). The SPB16.2 release contains the functionality for creating and automatically updating…

While simulating a VHDL design with Incisive Simulator, if an integer overflow is detected, the simulation stops with the following error message:

Error! integer overflow

File: ./test.vhd, line = 13, pos = 11

Scope: :$PROCESS_000

Time: 10 FS + 0

./test.vhd:13 i := i - 1;

Incisive is probably the only simulator to report such error condition. The only other popular VHDL simulator was not able to catch/report this condition, when…

Specmaniacs and Other Trailblazers,

The latest edition of the 'ClubT' newsletter is now posted here, and once again there is exciting news around e, Specman, and Verification.  Articles include:

* Have you heard of OVM e?

* Incisive 8.2 Technology Update

* Verification IP Portfolio E-x-p-a-n-s-i-o-n

Note: We did not send a newsletter out last October since we ran the 'ClubT' events then (with over 200 total attendees…

Drop by the Cadence booth at DesignCon to see the latest demonstrations of Allegro PCB SI for both serial link channel analysis as well as high-speed memory interface design verification.  In addition to other demos in the booth, be sure to mark your calendars for the Business Forum Panel,  Do It Right or Do It Over? Signal Integrity Engineers in the Era of Highly Compressed Project Schedules where industry professionals…

Those of you attending DesignCon in February should stop by the Cadence booth to see the latest integration of PakSi-E in SiP SI.  This integration not only supports signal integrity, but also there is new package power integrity technology.

We will also be showing techniques where Package-on-Package designs can be created, optimized, and analyzed.

I also hope you will drop by the Multi-Die Chip/Package Co-Design for SiP…

MMSIM 7.1 has just been released!

The following IC release GUIs support the new MMSIM7.1 features:

IC5.1.41.500.5.129 (However, USR6 or later is strongly recommended)
IC6.1.1 ISR65
IC6.1.3 ISR5
And later subversions.

In my last blog, I asked all of you to send me your design innovations. Thanks for your over-whelming response…and keep the emails coming in. And what better way to start the New Year than to talk about ST Microelectronics and its innovations!
 
I’m pretty darn sure that most you have heard about the company. But for those of you that haven’t, ST Microelectronics is a global leader in developing and delivering semiconductor…

Here in Cadence Product Marketing, we're still recovering from our very busy annual sales conference last week. Of course, I can't say much about what transpired there but I do want to comment that functional verification was a hot topic. In my many conversations with our field team, two trends were clear.

The first is that customers just can't afford to re-spin chips in the current economic climate. With the…

It seems that almost every semiconductor company is thinking or talking about 3D-IC stacking to boost functonal density & performance, reduce design size, reduce power consumption and hopefully reduce cost. An excellent summary of the 3D-IC design and its challenges was published recently by SCD Source and written by the popular long time industry writer Richard Goering (click here to read).  3D-IC when combined with…

As heralded in a prior posts, we recently hosted some "alumni" from our recent Techtorials, and other area customers, in a "deep dive" workshop focused exclusively on Metric Driven Verification (MDV) here on the San Jose campus. One of the architects of our MDV flow, and the creator of this specific workshop, is my colleague John Nehls. I've asked John to comment on how the program unfolded, and speak about…

As packages continue to increase in complexity, particularly in the arrangement of multiple wirebond die components in stacked and side-by-side arrangements, there is a growing need for the ability to ensure that the final product meets manufacturing and assembly requirements.

These checks may range from something as simple as the percentage of a bond wire’s length that is over the extents of the die, or may be as complex…

This week's installment of the "Exploring the Virtual Platform" series focuses on the Linux kernel that was booted in Part 1 of this series.

In Part 1, when QEMU was invoked to boot Linux there was a -kernel argument:     -kernel zImage.integrator

It's probably no secret this is the Linux kernel to run. It was directly downloaded from the QEMU download page. This was fine to show QEMU booting, but to do…

When compiling e files on top of Specman, or when using the save command, Specman stores its state in an .esv file.  However, there are times when the .esv file can become quite large -- sometimes on the order of 100s of MB.

The good news is that Specman allows you to control the compression level of its .esv file and save valuable disk space by setting the config flag "esv_compression_level".  Values for compression…

Last week, at Cadence Sales Kickoff, we have heard fascinating presentations from key US customer executives. The main points each one of the presenters made were:

1. The economy is slowing down and as a result many of the semiconductor (and fabless) companies are facing major challenges.

2. The successful semiconductor companies are the ones focusing on specific solution for their customers. This solution includes most of…

[Please welcome guest blogger Steve Hobbs, an Application Engineer in our Field Organization]

Hands-up those of you who hate creating and maintaining your vr_ad register definitions!

Pretty much all of you, I see...

No surprise really, as register maps get bigger and bigger, and with highly configurable design IP, you end up having several versions on the boil at once, each with a similar but not identical…

Back in November Cadence introduced a vastly expanded verification IP portfolio using the OVM.  By using the OVM, Cadence chose a methodology architected for multiple verification languages.  Beyond the fact that Cadence has the broadest IEEE standard support in the industry, why would any other company use a methodology and verification IP for use with multiple languages?

It turns out that each of the IEEE languages used…

Today I'm starting a series of articles related to what is commonly called the Virtual Platform or Virtual Prototype. There are probably many definitions of what it means, but I'm going to discuss the Virtual Platform as an abstract software model of a hardware system or subsystem created for the primary purpose of running embedded software and verifying the hardware/software interaction. A secondary purpose of the Virtual…

Last night the Electronic Design Automation Consortium ("EDAC", the trade group for the EDA industry) held its annual "CEO Forecast and Industry Vision" panel here in San Jose.  As with all prior EDAC events, I'm glad I went for both the networking (like seeing my old boss Larry Lapides of Imperas, and long time VA Partners like James Colgan, leader of the growing Xuropa EDA & electronics commun…

You might have seen the Generation Debugger of Specman's new Generation Engine IntelliGen in presentations or blogs (like Corey's blog on the testcase utility).  Let's go a little bit beyond the pictures and high level descriptions and have a look at the details of this new debugger.

First, a few words on the general concepts of Generation Debug:

• We first need to collect generation debug information
  • This needs…