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The new  UVM Multi-Language (ML) Open Architecture (OA) posted to the new UVMWorld is the result of a collaboration between Cadence and AMD.  It uniquely integrates e, SystemVerilog, SystemC, C/C+, and other languages into a cohesive verification hierarchy and runs on multiple simulators.  Moreover, the new solution is open for additional collaboration and technology enhancement. 

Since Cadence introduced ML verification four…

Flexible PCBs are used widely in everyday technology and electronics in addition to high-end, complex completed components. Two of the most prominent examples of flexible circuit usage are in hard disk drives and desktop printers. The following blog highlights the features of Allegro PCB Editor (Allegro) along with the Miniaturization option that provides a routing solution for flexible (flex) circuits.

Flexible Circuit…

We just completed some hugely successful Mixed-Signal Tech-on-Tours in North America. I am back in San Jose after this whirlwind trip that covered 9 cities in 4 weeks. Even though being on the road does get tedious, what kept me excited was the enthusiasm shown among Cadence customers for the Mixed-Signal Tech-on-Tour events. Close to 400 customers attended these Mixed-Signal Tech-On-Tour events.

The Dallas Mixed-Signal…

In previous releases, when you extract a net into SigXplorer, all the structures are automatically solved in Allegro PCB SI and then passed to SigXplorer. At times, the layerstack of the extracted structure might differ from the real layerstack in terms of the voids in a plane layer or shapes on the conducting layer. In such cases, the structure needs to be re-solved in SigXplorer. At other times, a field solution in…

This is first in a series of three blog posts that are going to present some powerful enhancements that were added to Specman 12.2 in order to ease the modeling of a multi-instance coverage environment. In this blog we're going to focus on the first enhancement, while the other two enhancements will be described in the following coverage blogs.

Starting with Specman 12.2, one can define the coverage options per subtype…

If you are attending the International Microwave Symposium (IMS 2013) in Seattle (June 2-7, 2013) stop by the Cadence Design Systems booth, #427.

We will be showing new MMSIM12.1.1 features including

• “Smart” HB GUI,
• Robust and easy to...

In my most recent posting, the particular subject was how to use SKILL++ to define a make_adder function. I commented in that article that the same thing would not work in traditional SKILL. In this posting, I'd like to walk…

Just a very "quick read" on a new option for Quickplace this week.

The Allegro PCB Editor Quickplace is an application used to ‘quickly’ scatter components around the perimeter of the design or to a room location. By default, components are placed not to overlap each other. As a result, the application may fail to place components if space is not available. A new control option in the 16.6 release,"Overlap components…

I'll confess: I didn't learn all of this strictly by browsing https://support.cadence.com/ (Cadence Online Support).  I also wandered over onto /blogs/ii (Industry Insights blog) and http://www.cadence.com/cadence/events (Cadence Events), which were well worth a look.

Application Note

1. Demystifying NCELAB

You've gotta love any technical document that begins with the word "demystifying".  Explains typical…

Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed on a large voltage, the resulting voltage loses its resolution, displaying staircase waveforms. With 64-bit precision, for the same signal, a perfect ramp waveform is displayed…

This article is dedicated to the gentleman I sat next to at lunch at CDNLive a while back who Is a CAD engineer busily supporting a large user community, but had been stumped by the question "How do I create a delta marker in VIVA?"

I'm sure he is not alone.  Delta markers in IC6.1.5 ViVA (Virtuoso Visualization and Analysis Tool) are very powerful, but they can be a bit hard to find and unless you read the…

Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation" button would stop the simulation both in an HDL context and in a Specman context if Specman was present in the simulation. To provide better flexibility in the exact place where you want to pause, the "Stop in Specman only" functionality has been introduced.  

As of IES 12.1,whenever Specman is present in the simulation…

Just a quick blog this week to mention a couple productivity enahancements for Capture-CIS. The 16.6 Allegro Design Entry CIS (Capture) product has a few new enhancements for Saving designs.

Read on for more details ...

Save

In the Hierarchy viewer, you’ll now see pages and library components which have been modified by the designer marked with an asterisk (“*”). These are schematics and pages that require saving prior to…

Assigning reference designators for the schematic instances is a very vital part of the entire PCB flow. This can sometimes become very cumbersome, and in some cases users allocate a major portion of their time and effort to get the assignments correct and optimized.

Annotation is the automated process of assigning reference designators in Allegro Design Entry CIS, also known as OrCAD Capture. The following AppNote clarifies…

Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required multiple executables:

–    Netassembler
–    Archiver
–    Purge
–    Packager

It was also less robust with dependencies on external programs, and the error resolution was not always clear.

With the 16.6 release, design migration is more efficient and less error prone. Below is a quick summary of what’s new in ADW 16.6 Design…

In the past several postings to this blog, we've looked at various ways to sum a given list of numbers. In this posting I'll present yet another way to do this. This time the technique will be markedly different than the previous ways, and will take advantage of a powerful feature of SKILL++, namely lexical closures. These closures will be used to implement data encapsulation, and we'll also use lexical closures…

In this blog post we are going to discuss 3 different cases where coding style can help you debug easier:

2.      Method Call Depth

Declarative vs. Sequential Coding

When modeling your testbench you will need to write code that describes time-consuming or complex steps of some intended behavior. This will be considered sequential…

The 16.6 Allegro FPGA System Planner (FSP) product has an extremely helpful Design Compare capability.

With design changes done in Allegro PCB Editor the FSP designer needs to verify and, if they agree, accept the PCB designer’s changes. The FSP Design Compare form compares two FSP designs and is similar, but not identical, to the one used in Allegro PCB Editor.

The Design Compare form

Design Compare is a stand-alone…

Applying ECOs to a design can be complex, stressful and error prone so it's important to apply the right tools and flow to implement the changes successfully. EDI System provides multiple ECO flows to physically implement ECOs efficiently and accurately based on your design requirements. And adding a tool such as Encounter Conformal ECO Designer or the Encounter Timing System's MMMC Signoff ECO capability can…