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Assigning reference designators for the schematic instances is a very vital part of the entire PCB flow. This can sometimes become very cumbersome, and in some cases users allocate a major portion of their time and effort to get the assignments correct and optimized.

Annotation is the automated process of assigning reference designators in Allegro Design Entry CIS, also known as OrCAD Capture. The following AppNote clarifies…

Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required multiple executables:

–    Netassembler
–    Archiver
–    Purge
–    Packager

It was also less robust with dependencies on external programs, and the error resolution was not always clear.

With the 16.6 release, design migration is more efficient and less error prone. Below is a quick summary of what’s new in ADW 16.6 Design…

In the past several postings to this blog, we've looked at various ways to sum a given list of numbers. In this posting I'll present yet another way to do this. This time the technique will be markedly different than the previous ways, and will take advantage of a powerful feature of SKILL++, namely lexical closures. These closures will be used to implement data encapsulation, and we'll also use lexical closures…

In this blog post we are going to discuss 3 different cases where coding style can help you debug easier:

2.      Method Call Depth

Declarative vs. Sequential Coding

When modeling your testbench you will need to write code that describes time-consuming or complex steps of some intended behavior. This will be considered sequential…

The 16.6 Allegro FPGA System Planner (FSP) product has an extremely helpful Design Compare capability.

With design changes done in Allegro PCB Editor the FSP designer needs to verify and, if they agree, accept the PCB designer’s changes. The FSP Design Compare form compares two FSP designs and is similar, but not identical, to the one used in Allegro PCB Editor.

The Design Compare form

Design Compare is a stand-alone…

Applying ECOs to a design can be complex, stressful and error prone so it's important to apply the right tools and flow to implement the changes successfully. EDI System provides multiple ECO flows to physically implement ECOs efficiently and accurately based on your design requirements. And adding a tool such as Encounter Conformal ECO Designer or the Encounter Timing System's MMMC Signoff ECO capability can…

The Allegro 16.6 Design Entry HDL release provides designers a mechanism to compare two databases for constraint differences. The databases that can be compared are of the following types:
• Schematics (.cpm)
• Layout design (.brd, .sip, .mcm)
• Constraints Manager Database (.dcf, .tcf)

The Constraint Comparison Utility can be used for comparing two different revisions/versions of the schematic or board databases…

Topics in March include advanced analysis in ADE GXL, taking advantage of lots of features for doing statistical analysis in ADE XL, defining bindkeys in ADE L (yes, you can do that!), plus a variety of useful details in the areas of routing and advanced custom layout.

Enjoy!

Application Notes

1. Design Tuning with Analog Design Environment GXL: Interactive and Automated Flows

Walks through a detailed example using several…

Beginning with the Allegro PCB Editor 16.6 release, you are provided a methodology to export a technology (.tcf) or constraints (.dcf) file which is a generic cross-section. A generic-cross-section file (GCSF) captures constraints for specific layer types. Currently, a GCSF supports four types of layers: TOP, INTERNAL (internal signal), PLANE, and BOTTOM.

Importing a GCSF will not update the design’s cross-section, but…

As in any…

The 16.6 Allegro RF PCB application has many new enhancements.

I’ll cover a few over the next several weeks. Here are some major autoplace related enhancements:

• Grouping in Design Entry HDL (DEHDL)
• Allegro PCB Editor Enhancements

Read on for more details …

Autoplace is a very important step for RF layout after the schematic is transferred to PCB layout. The system will automatically create groups based on connectivity…

At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face are in SoC level verification and seamless analog/digital implementation. Cadence has been addressing these challenges for…

When running power and rail analysis for a flip chip, we used to have to spend some time creating the voltage sources. It wasn't too terrible; usually we would output the bumps into a Cadence Encounter Digital Implementation (EDI) .io file, then use a perl script to filter out the pwr/gnd bumps and create the voltage source file format. The script would need a bit of editing from project to project, but nothing too complicated…

Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes/EDN Annual Creativity in Electronics (ACE) Awards in the Software Product of the Year category. In addition to IDA, Lip-Bu Tan and Cadence are also finalists for ACE Executive of the Year and Company of the Year, respectively.

Check out the Press Release.

The awards program honors the people and companies behind the technologies and products…

In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more efficient for design use. In addition, Allegro PCB Editor padstacks will be used to build the models.

Read on for more details …


Adding Vias

Adding a via is easier and faster than before. You no longer have to go through the Via Model Generator to create a model nor are you required to search the list of existing models that fit the…

In this episode of SKILL for the Skilled I'll introduce a feature of the let primitive that Scheme programmers will find familiar, but other readers may have never seen before. The feature is called named let, and I'll show you how to use it to sum the numbers in a given list.

Named LET

Feedback regulation loops are widely used by power electronic designers. It is one of the most important and sensitive parts of a power supply circuit. An incorrect feedback loop design may cause oscillations in the circuit, and also increase the output voltage droops. In order to achieve a stable and tight regulation in the output, it is important to have a correct feedback loop.

To test a feedback loop, generally engineers…

Cadence IC Packaging tools today provide a spreadsheet-based import mechanism for die and BGA (standard) components, as well as for importing of netlist updates. In certain design scenarios, particularly for leadframe package designs, it is also desirable to be able to import a similarly formatted file to define the bond wire connections in the design. In this way, when an updated component is brought into the design from…

February was a big month for RAKs (Rapid Adoption Kits)!  If you haven't checked out the listings under Resources->Rapid Adoption Kits yet, you're missing out.  You'll find databases with detailed instructions, documentation and videos on many tools, features and flows.   They've become very popular and we're adding more all the time.

We're also featuring content on routing, schematic PCells, ADE XL…

When you write a define-as or define-as-computed e macro, you sometimes need the replacement code to contain or to depend on the source information regarding the specific macro call, including the source module and the source line number.

For example, a macro may need to print source information, or it may need to create different code when used in one module than it needs to create when used in other modules.

You can…

With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done.  Here are some of the some of the highlights I took away from this informative event:

DVCon 2013 was a one stop shop for panels, papers, posters,
live demos, and tutorials on functional verification

* Great panels on Verification Planning…