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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

Building Verification Infrastructure for Complex PCIe Verification

Introduction PCIe (Peripheral Component Interconnect Express) is a high-speed serial…

• 4 min read
Verification IP , Functional Verification , PCIe , pcie gen6

Navigating Cache Coherence: The Back-Invalidate Feature in CXL 3.0

In the rapidly evolving landscape of data centers, ensuring cache coherence in multi…

• 2 min read
CXL , performance , Verification IP , Functional Verification , coherent , HIgh Speed Interconnect

Automate Regression Failure Triage with the Cadence Verisium

Have you ever experienced the frustration of fixing a bug during the design stage…

• 3 min read
Versium , Auto Triage , Regression

Revolutionize System Verification Flow with a Holistic Approach

The increasing functionality of designs is leading to a noticeable rise in the complexity…

• 3 min read
wholistic approach , system level , System Level Design Verification , verification

Ethernet Encryption: Harnessing the Power of IPSec Shields

In the ever-expanding domain of interconnected devices and digital communication…

• 2 min read

Leveraging AI to Optimize the Debug Productivity and Verification Throughput

The impact of semiconductors on various sectors cannot be overstated. Semiconductors…

• 5 min read

Insights Into the Evolutions and Optimizations of PCIe 6.0

The PCIe prot ocol (Peripheral Component Interconnect Express) had its first generation…

• 4 min read
Verification IP , VIP , PCIe , Optimize , pcie gen6 , PCIe 6.0

Maximise Verification Reuse with Cadence Perspec System Verifier

Are You Tired of Countless Hours Manually Creating Complex System-Level Coverage…

• 4 min read
verification reuse , perspec system verifier , Coverage Level Ststem Driven tests , system-level verification , SoC level test suit

USB4 Version 2.0 – Link Configurations

USB4 Version 2.0 specification was released by the USB Promoter Group earlier this…

• 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2 , usb4 router

Accelerate Your Debug with Verisium - Cadence's Next-Generation Debug Solution

Debugging low-power designs is its own unique challenge in the verification field…

• 3 min read
Low Power , Functional Verification , Verisium Debug , VerisiumDebug

Be Optimistic About Xcelium's New X-Pessimism App!

In simulation, X-Propagation has been used to track how unknown states or signals…

• 2 min read
Functional Verification , x-pessimism , xcelium , simulation

Verifying Compliance During PCIe Re-Timer Testing Poses Challenges

Verifying compliance during PCIe re timer testing poses challenges. Cadence PCIe…

• 4 min read
Re-timer , System Design and Verification , VIP , PCIExpress , compliance , Polling Compliance

USB4 Version 2.0 – Gen4 High-Speed Lane Initialization and Training

USB4 version 2.0 specifications were released by the USB Promoter Group earlier this…

• 3 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2 , usb4 router

Why Do You Need a Simulator-Friendly Debug Tool for UVM Debug?

UVM Testbench Today In 2011, UVM1.0 was introduced to the industry. It has already…

• 6 min read
uvm , debug , Testbench simulation , testbench , VerisiumDebug

Enhancing Network Security with MacSec: Protecting Ethernet Communications

The evolution of technology has led to a rapid increase in data transmission over…

• 2 min read
security , Automotive , Ethernet 800G , Verification IP , Ethernet VIP , Functional Verification , System Design and Verification , VIP , Ethernet standards , Automotive Ethernet , encryption , Ethernet , MacSec , Ethernet 400G , verification

Verification of Integrity and Data Encryption (IDE) for CXL Devices

In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe…

• 3 min read

The Crucial Need for Synchronization with Third-Party Systems

In today’s interconnected world, businesses and organizations rely heavily on various…

• 3 min read

Introducing PCIe's Integrity and Data Encryption Feature (IDE)

The Integrity and Data Encryption (IDE) was published in PCIe (Peripheral Component…

• 2 min read
Verification IP , encryption , PCIe , pcie gen6 , IDE

Unraveling the PCIe.6.0 Compliance Feature

In PCI Express (PCIe) devices, there is a need for testing near-worst-case inter…

• 4 min read
Verification IP , VIP , PCIe , feature , PCIe 6.0

Power Up Your Low-Power Verification - A Quick Overview

Handheld devices have evolved immensely over the past decade. Today's smartphones…

• 2 min read
Low Power , Verisium Debug , xcelium , verification

Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic Simulator…

Our previous posts in this series covered measuring parameters, switches, and profiling…

• 4 min read
cadence , Xcelium Logic Simulator , xcelium simulator , verification

Best Practices to Achieve the Highest Performance Using Xcelium Logic Simulator …

Xcelium Logic Simulator Profile Analysis Our previous post discussed measuring parameters…

• 4 min read
Xcelium Logic Simulator , profile analysis , xcelium simulator , xcelium , best practices , verification

Understanding PCIe 6.0 Shared Flow Control

As the data rate increases in PCIe 6.0, so do the challenges. If we talk in terms…

• 3 min read
SystemVerilog , Verification IP , PCIe , pcie gen6 , PCIe 6.0 , System Design and Verification , verification

CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performanc…

Xcelium mixed-signal simulation is part of Cadence’s verification full flow. The…

• 1 min read
Mixed-Signal , xcelium simulator , xcelium

Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic Simulator…

In a landscape characterized by increasingly intricate designs and rapidly diminishing…

• 5 min read
Xcelium Logic Simulator , Multi-Core , best practices , verification

Accelerate Design Debugging Using Verisium Debug

Verisium Debug is an advanced debugging tool that helps engineers explore, analyze…

• 1 min read
Verification IP , Verisium Debug , verification

Introduction of Precoding in PCIe 6.0

What Is Precoding in PCIe? With higher speed introduced from PCIe 5.0, high 32…

• 4 min read
Functional Verification , VIP , pcie gen6

Training Insights: Bridging the Skill-Gap with the New Cadence Training Digital IC…

The world is reeling towards AI/ML newer planes, and our EDA world is adding these…

• 2 min read
Functional Verification , System Design and Verification , Coverage-Driven Verification , place and route , digital flow , RTL2GDSII , Synthesis , digital_implementation
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