Featured

Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Veriest to Host Verification Meetup in Serbia Featuring Specman Macros

Veriest , a member of the Cadence Verification Alliance , is holding a series of…

• less than a min read
Specman , veriest , specman elite , verification

Cadence Announces Full Cadence Verification Suite Compatibility for Arm-Based High…

On October 16, 2018, Cadence Design Systems, Inc announced that, through a wide-reaching…

• 1 min read
press release , HPC , ARM , announcement

Learn How Valens uses Specman Macros Automate Configuration of Verification Environments…

Valens has achieved success through applying Specman to their verification projects…

• less than a min read
verification

Improving Your Testbench Flexibility with Enhanced Specman Templates

Cadence® Specman® Elite delivers faster and higher quality verification at block…

• less than a min read

Specman 18.09: Avoiding the Small Annoying Mistakes

Specman 18.09: Avoiding the Small Annoying Mistakes In almost every industry, one…

• 2 min read
enumerator , Specman , Functional Verification , e , e language , specman elite , xcelium

App Note Spotlight: Streamline Your SystemVerilog Code, Part IV - Dynamic Object…

Welcome back to the fourth installment of a special multi-part edition of the App…

• 2 min read
performance , SystemVerilog , Functional Verification , xcelium simulator

Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

Join us on September 14th for a free one-hour webinar on the finer aspects of the…

• less than a min read
uvm , Functional Verification , webinar , Duolos , uvm register layer

Adding a Patch Just in Time! — Or Can You Really Allow Yourself to Waste So Much…

One animation video - Patch Like The Wind - is worth a thousand words :) If you…

• 2 min read
Specman , Specman/e , Functional Verification , Specman e , tech tips , e language , team specman , save and restart

Evolution of DisplayPort

In 2006, the Video Electronics Standards Association (VESA) designed a new display…

• 2 min read
Verification IP , DisplayPort , verification

Tales From DAC: Netspeed and the Cadence Interconnect Workbench Pair Up

Services like facial detection, efficient cloud server workload management, artificial…

• 2 min read
cadence IWB , Interconnect Workbench , Functional Verification , gemini , netspeed

Is Ethernet Ready for the Automotive Market?

Consumer demand for advanced driver assistance and infotainment features are on the…

• 1 min read
Verification IP , VIP , Ethernet standards , Automotive Ethernet , IEEE 802.3 , Ethernet , TSN , Ethernet PHYs

Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server…

Learn about the challenges and solutions for integrating and verification PCIe(r…

• less than a min read

Tales from DAC: How Altia Systems Used Xcelium to Bring New Life to Virtual Meet…

We’re going to take a wild guess and say you’ve been in a meeting before. Maybe it…

• 2 min read
Functional Verification , DAC 2018 , Altia Systems , xcelium

Tales From DAC: How Syntiant Went From Zero to Tapeout in Six Months

Here’s something to chew on: Syntiant is an AI startup involved in deep learning…

• 2 min read
DAC , Functional Verification , syntiant , DAC 2018 , cadence cloud

Perspec Portable Stimulus Hands-On Workshop at DAC 2018

Cadence pulled a fast one at DAC 2018, almost like a bait and switch. We advertised…

• 1 min read
Perspec , AMIQ , pss , portable stimulus

AMIQ and Cadence demonstrate Accellera PSS v1.0 interoperability

There’s nothing like the heat of a DAC demo to stress new technology and the engineers…

• 2 min read
Perspec , perspec system verifier , AMIQ , Accellera , pss , portable stimulus

Is it Time to Verify Your Chips in the Cloud? Part 3 of 3

Welcome back to our series on cloud verification solutions. This is the final part…

• 2 min read
security , Functional Verification , cadence cloud , xcelium , palladium cloud

UVM-ML- Managers’ Freedom of Choice

Freedom of choice is a term we hear a lot, especially in the last 10 years. It is…

• 5 min read
Specman , Specman/e , UVM-ML , Specman e , UVM multi-language , UVM-e , UVM ML , multi-language , multi-language UVM , multi-language verification , verification

Is It Time to Verify Your Chips in the Cloud? Part 2 of 3

Welcome back to our series on cloud verification solutions. This is part two of a…

• 1 min read
uvm , Functional Verification , EDA , HPC , cadence cloud

App Note Spotlight: Streamline Your SystemVerilog Code, Part III - SystemVerilog…

Welcome back to the third installment of a special multi-part edition of the App…

• 2 min read
SystemVerilog , Tip , Functional Verification , App Note Spotlight

Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

Welcome to the first installment of a three-part blog series examining the issues…

• 2 min read
cloud-based verification , Functional Verification , cadence cloud , cloud computing

DMS 2.0 - What's Cool and What's New

Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)…

• 1 min read
digital mixed signal , Functional Verification , DMS 2.0 , xcelium simulator

Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load

Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic…

• 2 min read
SystemVerilog , uvm , Dynamic Test Load , Functional Verification , xcelium

PCI-SIG Developer's Conference: What's New with Gen 5 and When Will it be Adopted…

The release of PCIe 4.0 rev 1.0 in October 2017 was anticlimactic after the announcement…

• 3 min read
controller IP , Verification IP , PCIe Gen4 , PHY , PCIe , PCIe Gen5 , verification

RAK Attack: Verifying Power Intent for Low Power Mixed Signal SoCs

The wait is finally over—the Rapid Adoption Kit (RAK) for verifying the power intent…

• 2 min read
Low Power , Functional Verification , RAK , power intent , mixed signal

App Note Spotlight: Streamline Your SystemVerilog Code, Part II - SystemVerilog …

Welcome back to a special multi-part edition of the App Note Spotlight, where we…

• 2 min read
performance , SystemVerilog , Functional Verification , xcelium simulator

Empowering Generation - Range Generated Fields (RGF)

Specman constraints solver process consists of a series of reductions and assignments…

• 8 min read
Specman , Specman/e , Generation , e language , Constraints

Leading the Charge: Cadence Announces New Verification IP for UFS 3.0, CoaxPress…

Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence…

• 1 min read
hyperRAM , Functional Verification , coaxpress , UFS , press release
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