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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

Adding Annotations in Your e Code

If you have had a chance to work with languages like Java or C#, you might have come…

• 6 min read
Specman , e , e language , specman elite , annotations

Cadence and Arm Announce Early Access to Xcelium Parallel Logic Simulators on Arm…

On October 24, Cadence and Arm announced early access to the Xcelium Parallel Logic…

• 1 min read
Multi-Core , xcelium , ARM , simulation , announcement

Munich October 18—Come See SystemC Evolution Day!

Sorry, you missed Oktoberfest (which is mostly in September anyway). But come to…

• 2 min read
Munich , Functional Verification , Accellera , SystemC , event

Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 3 of…

Here we conclude the blog series and highlight the results of Mediatek 's use of…

• 1 min read
uvm , Perspec , coherent , perspec system verifier , coherency library , coherency , Accellera , mediatek , ARM , pss , portable stimulus

Teradyne Standardizes on Xcelium Simulator

Today, Cadence announced that Teradyne has adopted the Xcelium™ Parallel Simulator…

• less than a min read
Teradyne , ASIC , press release , xcelium , JasperGold , vManager

Teradyne "Formally" Adopts JasperGold FPV

CDNLive Boston 2017: Teradyne reveals their success with JasperGold in their presentation…

• 2 min read
Teradyne , FPV , CDNLive , customer success , JasperGold , Formal verification

Celebrating Five Years of Performance-Optimized Arm-Based SoCs: Now including AM…

It’s been quite a long 5-year journey building and deploying Performance Analysis…

• 2 min read
iwb , interconnect , amba5 , Interconnect Workbench , Palladium , Performance Analysis , AMBA , CoreLink , xcelium , ARM

When Arm meets Intel – Overcoming the Challenges of Merging Architectures on an SoC…

As the stakes for winning server segment market share grow ever higher an increasing…

• 2 min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Single Core vs. Multi Core: Simulation in Stereo

Latency simulations are the sworn enemy of the verification schedule. A handful of…

• 2 min read
Single-Core , Functional Verification , Multi-Core , xcelium , simulation

Making it Easier to Apply Palladium Z1 to SoC Performance Analysis

Recently, Renesas combined the Cadence® Interconnect Workbench, the Cadence vManager…

• 1 min read
Interconnect Workbench , customer feedback , success story , Palladium , Renesas

How to Get to a Trillion Devices in the Internet of Things in 2035

Next month at Arm TechCon, one of the key discussion topics with be the internet…

• 4 min read
prototyping , cadence , palladium z1 , IoT , Socrates , Emulation , Internet of Things , ARM , protium s1 , verification

How To Create L3 Cache Command Overflow Stress Test in Less Than 2 Days

One category of difficult SoC tests to create are stress tests, to validate the limits…

• 4 min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Put On Your Perspectacles: How Perspec Can Speed Up Your Testbench

It’s no secret that the bulk of time running simulations is spent on the testbench…

• 3 min read
Functional Verification , Perspec , xcelium , testbench

Do You Have The Tools You Need To Verify Your ARM Multi-core, Coherent SoC?

Multi-core, coherent SoCs are very complex and verifying their behavior requires…

• 1 min read
SoC verification , perspec system verifier , Accellera , ARM , pss , portable stimulus

Save & Restore with More: Preserve Your Entire SoC

The concept of Save and Restore is simple: instead of re-initializing your simulation…

• 3 min read
Functional Verification , x-team , update , xcelium simulator , feature , productivity , xcelium , save and restore

Infineon’s Coverage-Driven Distribution: Shortcutting the MDV Loop

There are more ways to improve productivity in the verification process than simply…

• 3 min read
Specman , CDD , CDNLive , Infineon , Functional Verification , e language , efficiency , MDV

How to Model State Machines in the Accellera Portable Stimulus Standard for Low Power…

The Accellera Portable Stimulus Standard (PSS) is experiencing growing customer interest…

• less than a min read
Low Power , SoC verification , perspec system verifier , Accellera , pss , portable stimulus

X-Propagation: Xcelium Simulator’s X-prop Technology Ensures Deterministic Reset

All chips need to cold reset on every power-up. Warm resets, however, are a bit more…

• 2 min read
SystemVerilog , Functional Verification , xcelium , Reset , simulation

Moving to Xcelium Simulation? I’m Glad You Asked

Ready to take the next step in simulation technology with a true third-generation…

• 2 min read
performance , Self-Help , uvm , simvision , RAK , Multi-Core , Appnote , troubleshooting , simulation , Cadence support

ROHM CO., Ltd Adopts Our Functional Safety Verification Solution

On July 17, 2017, Cadence announced that the Cadence® Functional Safety Verification…

• less than a min read
functional safety , Functional Verification , ROHM Co. , press release , ISO 26262

Xperiences with Xcelium: Hewett-Packard Enterprise Makes the Switch

At Hewlett-Packard Enterprise (HPE), the team working to create IP for “The Machine…

• 1 min read
Functional Verification , xcelium , hp enterprise

Enum compatibility error in Specman

One of my favorite quotes about SW programming is the following by Edsger Dijkstra…

• 4 min read
enumerator , Specman , Incisive , e language , xcelium , verification

Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 2 of…

Here we go through the application of Cadence Perspec™ System Verifier by Mediatek…

• 1 min read
uvm , Perspec , coherent , perspec system verifier , coherency library , coherency , Accellera , mediatek , ARM , pss , portable stimulus

Mediatek Deploys Perspec for SoC Verification of Low Power Management

Mediatek has been using the Cadence Perspec™ System Verifier for their SoC level…

• 2 min read
uvm , Perspec , coherent , perspec system verifier , coherency library , coherency , Accellera , mediatek , ARM , pss , portable stimulus

Cadence @ DAC: What to Expect and What to See

Cadence returns to DAC 2017 this year, showcasing our full verification suite. Here…

• 3 min read
DAC , methodology , EDA , Formal verification , verification

New VIP for ARM AMBA 5 CHI Issue B

In coordination with the announcement of the new ARM® AMBA® 5 Coherent Hub Interface…

• 3 min read
Verification IP , VIP , AMBA , ARM , CHI VIP

See Perspec Running Accellera Portable Stimulus Examples Here and Now!

Accellera has announced the release of an Early Adopter specification of the Portable…

• less than a min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Accellera Has Done It Again! Portable Stimulus Standard Available For Review

In a press release this morning, Accellera announced availability of an Early Adopter…

• 2 min read
CDNS , Perspec , Accellera , pss , portable stimulus
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