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Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Arm Zena CSS – Accelerating Chiplet-Based SoC Design for AI-Defined Vehicles

Cadence is collaborating with Arm on their groundbreaking first-generation compute…

Robert
• 6 min read
virtual prototyping , ucie , featured , chiplet , virtual platform
SoC and IP

Latest blogs

Link Training: Establishing Link Communication Between DisplayPort Source and Sink…

Link training is the first stepping stone to enabling the communication channel between…

• 2 min read
Verification IP , VIP , DisplayPort , Link Training , Design IP and Verification IP

ARM-Cadence IP Deal Propels Engineering Innovation Ahead: Martin Lund

On March 18, Cadence and ARM announced a groundbreaking deal that provides reciprocal…

• 6 min read
IP , electronic system design , cadence , systems engineering , IP design , ip cores , interoperability , ARM

Mobile World Congress: Two New Audio IP Announcements

BARCELONA, Spain—Mobile World Congress is not surprisingly focused on mobile devices…

• less than a min read
DTS , #MWC15 , cadence , audio , audio subsystems , Mobile World Congress , IP design , Tensilica , HiFi Audio , MaxxVoice

IP Requirements for Verifying CHI-Based Designs

Just as IP components offload design effort, verification IP (VIP) components offload…

• 2 min read
Verification IP , Interconnect Validator , IVD , CHI , VIP , Design IP and Verification IP , CHI VIP

Mobile World Congress: A Decade of Change in IP Innovation

BARCELONA, Spain—In the past decade, immense change has come to mobile electronic…

• 1 min read
electronic system design , #MWC15 , cadence , Steve Roddy , Mobile World Congress , Tensilica , mobile , IC design

WiGig Has Arrived to Enable IoT Designs--and Cut the HDMI Cord!

What is WiGig WiGig is the name given to a high-speed multi-gigabit wireless communications…

• 3 min read
wireless , cadence , IP blocks , IP design , WiGig IP , 802.11ad , wiGig , HDMI , WiFi

Looking Forward to MWC – Hope to See You There

This year’s Mobile World Congress (MWC) in Barcelona, March 2-5, should be the largest…

• 1 min read
DSP , IP , MIPI , Mobile World Congress , Tensilica , Tensilica IP , image processing , video processing , MWC 2015

Yes! Full 2-Day IP Track at CDNLive Silicon Valley

CDNLive Silicon Valley 2015 will be held Tuesday and Wednesday, March 10-11, at the…

• less than a min read
IP , DDR4 , CDNLive

Increased CHI Coherency Verification Challenges

Cache coherency is not unique to the new ARM® AMBA® 5 CHI (Coherent Hub Interface…

• 2 min read
Verification IP , Interconnect Validator , IVD , CHI , VIP , Dimitry Pavlovsky , Design IP and Verification IP , CHI VIP

Where’s My Star Trek Lifestyle?

The sparkle seems to have gone out of the Internet of Things (IoT) market for the…

• 2 min read
Smarthome , cadence , IP blocks , IoT , wearables , IP design , embedded design , robotics , embedded systems

HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF

High-performance and high-speed memory design characterized by low-power operation…

• 2 min read
DDR4 , electronic system design , cadence , IP blocks , TSMC , 16nm , FinFET , Hisilicon

Cadence at CES 2015: Enabling Surreal Surround Sound Audio

LAS VEGAS—In the cacophony of CES, it’s refreshing to find an escape. I found mine…

• 1 min read
DTS , Consumer Electronics , cadence , surround sound , audio , Tensilica , HiFi DSP , CES 2015 , mobile

Cadence Firmware Packages Enable Successful IP Integration

Building a system on chip (SoC) from IP blocks requires system-level integration…

• 3 min read
Bring-up , IP integration , ip cores , firmware

Get a Glimpse at New Ethernet Standards in the Works

I attended the IEEE 802.3 meeting in Atlanta last week. I have blogged about Ethernet…

• 2 min read
25G Ethernet , new Ethernet standards , Ethernet standards , Automotive Ethernet , IEEE 802.3 , ip cores , Ethernet

Cadence at CES 2015: Power-Sensitive Always-On Systems

LAS VEGAS—As the mobile world matures, opportunities abound for optimizing the user…

• less than a min read
audio , power management , HiFi Mini , Tensilica , Realtek Semiconductor , HiFi DSP , CES 2015

Cadence at CES 2015: A Look at Face-Detection Technology

LAS VEGAS—A key function of automotive, IoT, security, and similar applications is…

• less than a min read
IP , cadence , IVP , Xtensa , CES 2015 , image processing , video processing

Cadence at CES 2015: The IP Story

LAS VEGAS—The annual International Consumer Electronics Show (CES) here is not just…

• less than a min read
ip cores semiconductor IP , EDA companies , Martin Lund , IP design , CES 2015

My Top 10 List from CES

After nearly a week at CES, almost everyone is asking me – what was the big thing…

• 4 min read
DSP , Design IP , IP , CES , audio , video , IoT , HiFi , ip cores , Tensilica , semiconductor IP , Internet of Things , imaging

Cadence at CES 2015: Experience Integrated Solutions for Mobile

Given that CES is a novelty-focused event, it is crucial that innovative companies…

• 2 min read
Design IP , cadence , Consumer Electronics Show , CES , DIP , DSI , Tensilica , CES 2015 , MIPI D-PHY

Driven by Mobile, LPDDR4 Poised to Step Up

SANTA CLARA, Calif.—In the long and storied history of semiconductor memories, the…

• 2 min read
IP , DDR4 , MemCon 2014 , IoT , IP integration , memory IP , ip cores , future of IP

USB Power Delivery Is Better with Type-C

In my previous blog post , I wrote how much better than the existing Type-A and Type…

• 2 min read
USB 3.0 , Design IP , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Its Name is C, Type-C: The New Superhero of Cables from USB

Isn’t it interesting how, with time, all the nitty-gritty of technology is starting…

• 2 min read
Design IP , IP , Jacek Duda , USB , ip cores , USB3.0

Call for Papers Now Open – CDNLive Silicon Valley

CDNLive Silicon Valley (March 10-11, 2015, Santa Clara Convention Center) provides…

• less than a min read
IP , EDA conference , CDNLive , IP papers , EDA papers

IoT Focus: IoT Applications Require a New Architectural Vision

I wrote earlier that the sheer vastness and potential for IoT designs require a different…

• 3 min read
Consumer Electronics , IoT , IP integration , ip cores , Internet of Things , Seow Yin Lim , interface design , user interface

How Do You Build a Wi-Fi 802.11ac Programmable Modem?

The Tensilica® group at Cadence has just published a 37-page application note on…

• 1 min read
Wi-Fi 802.11ac transceiver , Tensilica DSPs , WLAN , LTE , programmable modem

IoT Focus: Wrestling with the Design, Time to Market, and Cost Challenges of IoT

You know we live in astonishing times when you can start your car by talking into…

• 2 min read
Consumer Electronics , cadence , IoT , IP integration , IOT applications , ip cores , Internet of Things , Seow Yin Lim , interface design , user interface

Highlights from Recent IEEE 802.3 Ethernet Standards Meeting

I wanted to share with you a number of updates from last month's IEEE 802.3 meeting…

• 2 min read
25G Ethernet , Ethernet standards , Automotive Ethernet , IEEE 802.3 , Ethernet

IoT Focus: Natural User Interface Design Crucial to Success

Each era of electronics innovation is generally marked by a dominant end application…

• 2 min read
Consumer Electronics , cadence , IoT , IP integration , IOT applications , ip cores , Internet of Things , Seow Yin Lim , interface design , user interface
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