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Accelerating Chiplet Innovation with a New Partner Ecosystem

The semiconductor industry is currently undergoing a massive shift. As we push the…

Mick Posner
• 4 min read
IP , featured , chiplets , physical ai , OCP FCSA

The Memory Imperative for Next-Generation AI Accelerator SoCs

The tremendous growth in large language model (LLM) size corresponds with an equally…

Subash Peddu
• 4 min read
featured , HBM , SoC , AI

Scale-Up and Scale-Out IP for Optical Interconnect for Accelerated Computing

Optical connectivity is foundational to modern data centers, enabling high-bandwidth…

HW202512191014
• 4 min read
featured , AI data center , AI factory , Data Center architecture
SoC and IP
Latest blogs

Cadence IP for USB Works over Type-C (Proof Inside)

There is no other specification in the history of USB that caused so much discussion…

• 1 min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Electrical Validation of DDR4 Interfaces

Developing SoCs with high-speed memory interfaces, such as DDR4, presents substantial…

• 1 min read
Design IP , DDR4 , LPDDR , DDR , Sigrity , Tektronix

Cadence ONFI 4.0 Flash Memory IP Increases Data Access to 800Mtps and Reduces Power…

Announcing Availability of ONFI 4.0 IP Flash memory applications have expanded…

• 2 min read
QSPI , flash , ONFI , USB , SD , eMMC , ip cores , ECC

USB Type-C Interoperability Workshop—True, Real-Life Validation

There’s no denying that USB Type-C is the fastest adopted specification in the history…

• 1 min read
USB Type-C , DisplayPort , Alternate Mode

Call for Papers for MemCon Closes This Friday

You still have a chance to get a paper accepted at the premier conference for memory…

• less than a min read
MemCon , memory technology , ip cores , memories

Find Everything You Need to Build an Advanced PCI Express 4.0 Solution in One Booth…

The PCI-SIG Developers Conference happening today and tomorrow will be yet another…

• 2 min read
PCIe Gen4 , pcie gen2 , 16nm , PCIe Gen3 , PCI-SIG

Sensor Processing, How Hard Can It Be?

When I think back back just a few years ago, there were only a handful of devices…

• 2 min read
DSP , IP , IP blocks , controller , IoT , SoC , Fusion , ip cores , Processor IP , Tensilica , semiconductor IP , Internet of Things , Design IP and Verification IP , always-on

Tensilica Team Wins DAC 2015 Best Paper Award

Cadence’s Tensilica team was honored with the Best Paper Award at the IP track at…

• 1 min read
IP , Chris Rowen , ip cores , vision , imaging , image processing

Three Steps for USB Application Success – Design, Verify, Certify

With the USB protocol being so popular nowadays (and frankly speaking, was there…

• 2 min read
Design IP , host , cadence , controller , PHY , OTG , USB , Dual Mode , ip cores , Dual Role , device

IP is BIG at the Design Automation Conference, June 7-11, in San Francisco

Think that DAC is all about EDA tools? Not anymore. This year there are over 100…

• 2 min read
controller IP , Verification IP , DSP , Design IP , IP , Chris Rowen , Rowen , IP blocks , ip cores , Tensilica , DAC 2015 , Design IP and Verification IP

How to Design to the ‘Always-on’ IoT Imperative

I’ll never forget covering a presentation that then-National Semiconductor CEO Brian…

• 2 min read
IP , Chris Rowen , cadence , IoT , Fusion , Tensilica , Internet of Everything. , Internet of Things

Speed, Function, and Technology as Key Factors for USB Applications

USB is regarded as the world’s most popular serial interface, with over 1 billion…

• 2 min read
Design IP , host , controller , PHY , OTG , 1.1 , USB , Dual Mode , ip cores , 2.0 , Dual Role , device , 3.0

Don’t Miss Embedded Vision Summit on May 12

One of the best, most insightful (no pun intended) conferences each year is the Embedded…

• 1 min read
DSP , Chris Rowen , IVP , vision processing , embedded vision , Tensilica , vision

Next-Generation DDR4 and LPDDR4 IP in TSMC 16FF+ Enable 200Gb+ Data Transfers for…

Consumer demand for entertainment and communication is changing the architecture…

• 5 min read
DDR4 , LPDDR4 , IoT , cloud , Design IP and Verification IP , 16FF+

CDNLive IP Track Presentations Available Online

With more than 100 presentations, live product demos, designer expo, and numerous…

• 2 min read
CDNLive , Tensilica , Design IP and Verification IP

Interconnect Validator and its Significance

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP…

• 2 min read
Interconnect Workbench , AMBA ACE , Interconnect Validator , VIP , AMBA CHI , SoC , OCP , Design IP and Verification IP

Sign Up for Linley Mobile Conference – See Chris Rowen

If you’ve never heard of the Linley Mobile Conference , you’ve been missing out on…

• 1 min read
wireless , sensor fusion , always on , always alert , sensors , Fusion , Tensilica , sensing , Linley Mobile Conference , context triggers

Call for Papers for MemCon Now Open

What’s the biggest conference for everything related to memories? If you answered…

• 1 min read
Verification IP , DDR4 , MemCon , LPDDR , VIP , memory IP , Denali , Design IP and Verification IP , memories

Mobile World Congress: Enabling Systems with Sensor Fusion, DSPs

BARCELONA, Spain—We hear a lot about sensor fusion and the applications that it can…

• 1 min read
DSP , sensor fusion , #MWC15 , cadence , Freespace , Mobile World Congress , Tensilica , Hillcrest Labs

Link Training: Establishing Link Communication Between DisplayPort Source and Sink…

Link training is the first stepping stone to enabling the communication channel between…

• 2 min read
Verification IP , VIP , DisplayPort , Link Training , Design IP and Verification IP

ARM-Cadence IP Deal Propels Engineering Innovation Ahead: Martin Lund

On March 18, Cadence and ARM announced a groundbreaking deal that provides reciprocal…

• 6 min read
IP , electronic system design , cadence , systems engineering , IP design , ip cores , interoperability , ARM

Mobile World Congress: Two New Audio IP Announcements

BARCELONA, Spain—Mobile World Congress is not surprisingly focused on mobile devices…

• less than a min read
DTS , #MWC15 , cadence , audio , audio subsystems , Mobile World Congress , IP design , Tensilica , HiFi Audio , MaxxVoice

IP Requirements for Verifying CHI-Based Designs

Just as IP components offload design effort, verification IP (VIP) components offload…

• 2 min read
Verification IP , Interconnect Validator , IVD , CHI , VIP , Design IP and Verification IP , CHI VIP

Mobile World Congress: A Decade of Change in IP Innovation

BARCELONA, Spain—In the past decade, immense change has come to mobile electronic…

• 1 min read
electronic system design , #MWC15 , cadence , Steve Roddy , Mobile World Congress , Tensilica , mobile , IC design

WiGig Has Arrived to Enable IoT Designs--and Cut the HDMI Cord!

What is WiGig WiGig is the name given to a high-speed multi-gigabit wireless communications…

• 3 min read
wireless , cadence , IP blocks , IP design , WiGig IP , 802.11ad , wiGig , HDMI , WiFi

Looking Forward to MWC – Hope to See You There

This year’s Mobile World Congress (MWC) in Barcelona, March 2-5, should be the largest…

• 1 min read
DSP , IP , MIPI , Mobile World Congress , Tensilica , Tensilica IP , image processing , video processing , MWC 2015

Yes! Full 2-Day IP Track at CDNLive Silicon Valley

CDNLive Silicon Valley 2015 will be held Tuesday and Wednesday, March 10-11, at the…

• less than a min read
IP , DDR4 , CDNLive

Increased CHI Coherency Verification Challenges

Cache coherency is not unique to the new ARM® AMBA® 5 CHI (Coherent Hub Interface…

• 2 min read
Verification IP , Interconnect Validator , IVD , CHI , VIP , Dimitry Pavlovsky , Design IP and Verification IP , CHI VIP
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