Featured

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Arm Zena CSS – Accelerating Chiplet-Based SoC Design for AI-Defined Vehicles

Cadence is collaborating with Arm on their groundbreaking first-generation compute…

Robert
• 6 min read
virtual prototyping , ucie , featured , chiplet , virtual platform
SoC and IP

Latest blogs

Word from the Source—USB-IF on What USB-IF Is and What’s New in USB (Jeff Ravencraft…

In case you don’t know, USB Implementers Forum (USB-IF, for short) is the organization…

• less than a min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Will USB Type-C Connector Replace the 3.5mm Audio Jack?

In the past few days, there have been many posts on the Internet around Apple planning…

• 1 min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , Design IP and Verification IP , USB connector , USB 3.1

50 Gbps Ethernet is on the Way

Here is my report from the most recent IEEE 802.3 standards meeting, which was held…

• 2 min read
Ethernet standards , Automotive Ethernet , IEEE 802.3 , Ethernet , Marris , 50G Ethernet

Lowering Energy Consumption in Always-on IoT Designs

As a lead design engineer on the Tensilica R&D team, Dr. Avinash Lingamneni certainly…

• 5 min read
Low Power , always on , IoT , wearable , Tensilica , mobile

Cadence Ports LPDDR4/DDR4 Combo PHY to TSMC 28HPC to Serve Rapid Adoption in Consumer…

Rapid consumer product revolution continues to be enabled by semiconductor technology…

• 1 min read
DDR4 , LPDDR4 , MemCon , LPDDR , DDR , DDR3 , LPDDR3

USB Developer Days – Turning Specifications into Applications

Each time I start working on an introductory paragraph for a new USB blog entry,…

• 2 min read
USB 3.0 , cadence , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Ethernet Reaches into Ever More Application Spaces

I blog from time to time about what’s new in Ethernet. I have just returned from…

• 2 min read
HDD , 802.3bs , Automotive Ethernet , Ethernet , Design IP and Verification IP , Ethernet PHYs

Cadence Announces the First MIPI I3C Verification IP!

The MIPI Alliance has developed dozens of specifications, standardizing all interfaces…

• 1 min read
Verification IP , MIPI Alliance , MIPI , Design IP and Verification IP

USB Type-C Ecosystem, Issues, and Opportunities

USB Type-C is an innovation that is transforming the electronics industry. What is…

• less than a min read
USB Type-C , DisplayPort , MCCI , Alternate Mode

Cadence IP for USB Works over Type-C (Proof Inside)

There is no other specification in the history of USB that caused so much discussion…

• 1 min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Electrical Validation of DDR4 Interfaces

Developing SoCs with high-speed memory interfaces, such as DDR4, presents substantial…

• 1 min read
Design IP , DDR4 , LPDDR , DDR , Sigrity , Tektronix

Cadence ONFI 4.0 Flash Memory IP Increases Data Access to 800Mtps and Reduces Power…

Announcing Availability of ONFI 4.0 IP Flash memory applications have expanded…

• 2 min read
QSPI , flash , ONFI , USB , SD , eMMC , ip cores , ECC

USB Type-C Interoperability Workshop—True, Real-Life Validation

There’s no denying that USB Type-C is the fastest adopted specification in the history…

• 1 min read
USB Type-C , DisplayPort , Alternate Mode

Call for Papers for MemCon Closes This Friday

You still have a chance to get a paper accepted at the premier conference for memory…

• less than a min read
MemCon , memory technology , ip cores , memories

Find Everything You Need to Build an Advanced PCI Express 4.0 Solution in One Booth…

The PCI-SIG Developers Conference happening today and tomorrow will be yet another…

• 2 min read
PCIe Gen4 , pcie gen2 , 16nm , PCIe Gen3 , PCI-SIG

Sensor Processing, How Hard Can It Be?

When I think back back just a few years ago, there were only a handful of devices…

• 2 min read
DSP , IP , IP blocks , controller , IoT , SoC , Fusion , ip cores , Processor IP , Tensilica , semiconductor IP , Internet of Things , Design IP and Verification IP , always-on

Tensilica Team Wins DAC 2015 Best Paper Award

Cadence’s Tensilica team was honored with the Best Paper Award at the IP track at…

• 1 min read
IP , Chris Rowen , ip cores , vision , imaging , image processing

Three Steps for USB Application Success – Design, Verify, Certify

With the USB protocol being so popular nowadays (and frankly speaking, was there…

• 2 min read
Design IP , host , cadence , controller , PHY , OTG , USB , Dual Mode , ip cores , Dual Role , device

IP is BIG at the Design Automation Conference, June 7-11, in San Francisco

Think that DAC is all about EDA tools? Not anymore. This year there are over 100…

• 2 min read
controller IP , Verification IP , DSP , Design IP , IP , Chris Rowen , Rowen , IP blocks , ip cores , Tensilica , DAC 2015 , Design IP and Verification IP

How to Design to the ‘Always-on’ IoT Imperative

I’ll never forget covering a presentation that then-National Semiconductor CEO Brian…

• 2 min read
IP , Chris Rowen , cadence , IoT , Fusion , Tensilica , Internet of Everything. , Internet of Things

Speed, Function, and Technology as Key Factors for USB Applications

USB is regarded as the world’s most popular serial interface, with over 1 billion…

• 2 min read
Design IP , host , controller , PHY , OTG , 1.1 , USB , Dual Mode , ip cores , 2.0 , Dual Role , device , 3.0

Don’t Miss Embedded Vision Summit on May 12

One of the best, most insightful (no pun intended) conferences each year is the Embedded…

• 1 min read
DSP , Chris Rowen , IVP , vision processing , embedded vision , Tensilica , vision

Next-Generation DDR4 and LPDDR4 IP in TSMC 16FF+ Enable 200Gb+ Data Transfers for…

Consumer demand for entertainment and communication is changing the architecture…

• 5 min read
DDR4 , LPDDR4 , IoT , cloud , Design IP and Verification IP , 16FF+

CDNLive IP Track Presentations Available Online

With more than 100 presentations, live product demos, designer expo, and numerous…

• 2 min read
CDNLive , Tensilica , Design IP and Verification IP

Interconnect Validator and its Significance

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP…

• 2 min read
Interconnect Workbench , AMBA ACE , Interconnect Validator , VIP , AMBA CHI , SoC , OCP , Design IP and Verification IP

Sign Up for Linley Mobile Conference – See Chris Rowen

If you’ve never heard of the Linley Mobile Conference , you’ve been missing out on…

• 1 min read
wireless , sensor fusion , always on , always alert , sensors , Fusion , Tensilica , sensing , Linley Mobile Conference , context triggers

Call for Papers for MemCon Now Open

What’s the biggest conference for everything related to memories? If you answered…

• 1 min read
Verification IP , DDR4 , MemCon , LPDDR , VIP , memory IP , Denali , Design IP and Verification IP , memories

Mobile World Congress: Enabling Systems with Sensor Fusion, DSPs

BARCELONA, Spain—We hear a lot about sensor fusion and the applications that it can…

• 1 min read
DSP , sensor fusion , #MWC15 , cadence , Freespace , Mobile World Congress , Tensilica , Hillcrest Labs
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