• Discussion

  leLayerSize didn't work for pcell, is there any way around it? Locked

  3151 views
  6 replies
  Latest over 15 years ago
  by kpai
• Discussion

  assert results Locked

  15472 views
  2 replies
  Latest over 15 years ago
  by jshafer
• Discussion

  Getting critical path extraction from encounter to spice Locked

  15294 views
  3 replies
  Latest over 15 years ago
  by Kari
• Discussion

  No connection between VSS/VDD pins and PW ring Locked

  5456 views
  6 replies
  Latest over 15 years ago
  by Kari
• Discussion

  NanoRoute: DRC / LVS issues Locked

  24043 views
  11 replies
  Latest over 15 years ago
  by Kari
• Discussion

  Monte Carlo simulation correlations definition puzzle Locked

  15306 views
  5 replies
  Latest over 15 years ago
  by lunren
• Discussion

  Select pins and pin label by SKILL. Locked

  21438 views
  9 replies
  Latest over 15 years ago
  by ashkumar
• Discussion

  Doubts on Hierarchical schematic design Locked

  13375 views
  2 replies
  Latest over 15 years ago
  by Linga
• Discussion

  About AgeMOS model for RelXpert simulation Locked

  14663 views
  1 reply
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  Insufficient memory Locked

  20803 views
  6 replies
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  Create mulitpart path with 2 row of contacts Locked

  18175 views
  5 replies
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  Tcl Commands to set method of Integration Locked

  14823 views
  1 reply
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  How to change NMOS Internal Gate Connection by using SKILL ? Locked

  14361 views
  1 reply
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  LVS Matching error Locked

  19122 views
  5 replies
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  functional coverage result issue at the end of simulation Locked

  13737 views
  1 reply
  Latest over 15 years ago
  by StephenH