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Custom IC Design

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  • Discussion

    mtline 2D solver ignoring dlosstype/dloss

    Category: Custom IC Design

    By drdanmc

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    updated over 5 years ago by Andrew Beckett

    1 replies • 1149 views
  • Discussion

    Simulation of an inverter using FinFETs

    Category: Custom IC Design

    By pradeep22

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    updated over 5 years ago by Andrew Beckett

    1 replies • 15384 views
  • Discussion

    What does such sign mean in the data view

    Category: Custom IC Design

    By sjwprc

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    updated over 5 years ago by sjwprc

    3 replies • 14168 views
  • Discussion

    Unable to attach technology library?

    Category: Custom IC Design

    By emax

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    updated over 5 years ago by Andrew Beckett

    7 replies • 21466 views
  • Discussion

    GPDK045

    Category: Custom IC Design

    By analogy

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    updated over 5 years ago by Andrew Beckett

    5 replies • 18113 views
  • Discussion

    DSPF file disregard in extracted simulation

    Category: Custom IC Design

    By ZoltanT

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    updated over 5 years ago by ZoltanT

    7 replies • 24801 views
  • Discussion

    Compare two LEF files

    Category: Custom IC Design

    By Sherl

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    updated over 5 years ago by Sherl

    4 replies • 17009 views
  • Discussion

    How to properly shutdown virtuoso?

    Category: Custom IC Design

    By chaujohnthan

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    updated over 5 years ago by chaujohnthan

    4 replies • 19160 views
  • Discussion

    Spectre: is it possible to specify initial conditions for DSPF blocks?

    Category: Custom IC Design

    By dontpanic

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    updated over 5 years ago by dontpanic

    2 replies • 15977 views
  • Discussion

    Determining the sings for the DC Operating Points in ADE XL

    Category: Custom IC Design

    By wgtkan

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    updated over 5 years ago by wgtkan

    2 replies • 14723 views
  • Discussion

    Global net name mapping for spectre netlist

    Category: Custom IC Design

    By Amar Kumar

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    updated over 5 years ago by Amar Kumar

    2 replies • 15804 views
  • Discussion

    Calculator stack--swap? dup?

    Category: Custom IC Design

    By smiff

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    updated over 5 years ago by smiff

    4 replies • 1690 views
  • Discussion

    EvalType in Cadence ADEXL

    Category: Custom IC Design

    By NorNand

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    updated over 5 years ago by Andrew Beckett

    1 replies • 16347 views
  • Discussion

    error during creating the netlist from layout using 45nm technolgy

    Category: Custom IC Design

    By vinod joshi

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    updated over 5 years ago by Andrew Beckett

    3 replies • 22881 views
  • Discussion

    FreePDK15 setup/layout problem

    Category: Custom IC Design

    By Greeny

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    •

    updated over 5 years ago by Andrew Beckett

    4 replies • 2957 views
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