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Custom IC Design

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  • Discussion

    Specify a file path as a parameter type in Cadence VerilogAMS

    Category: Custom IC Design

    By uzzy

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    updated over 11 years ago by Andrew Beckett

    4 replies • 16972 views
  • Discussion

    Sweeping Vth vs L

    Category: Custom IC Design

    By Arjun RP

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    •

    updated over 11 years ago by Arjun RP

    24 replies • 32502 views
  • Discussion

    TSMC 65nm Reference Design Kit

    Category: Custom IC Design

    By xy318575767

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    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 15367 views
  • Discussion

    Netlisting fails as symbol is not an instance. (RESOLVED)

    Category: Custom IC Design

    By bpdegnan

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    started over 11 years ago

    0 replies • 14601 views
  • Discussion

    virtuoso possible outputs in IC610

    Category: Custom IC Design

    By jagdev

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    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 13849 views
  • Discussion

    VerilogA definitions from ADE-XL

    Category: Custom IC Design

    By daasboe

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    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 14056 views
  • Discussion

    Monte Carlo Simulation Failure

    Category: Custom IC Design

    By Jordan Morris

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    •

    updated over 11 years ago by Andrew Beckett

    2 replies • 15676 views
  • Discussion

    Virtuoso ADE Dynamic Parameter Clarification

    Category: Custom IC Design

    By jjang3

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    updated over 11 years ago by jjang3

    4 replies • 15509 views
  • Discussion

    Faster way to move instances

    Category: Custom IC Design

    By Lynks

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    •

    updated over 11 years ago by Lynks

    2 replies • 15875 views
  • Discussion

    leChopShape is IC616

    Category: Custom IC Design

    By NKU10k

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    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 13902 views
  • Discussion

    Does Spectre (Currnetly : Version 13.1.0.127.ISR3) has any option or setup to get better SFDR ?

    Category: Custom IC Design

    By Charley Chen

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    updated over 11 years ago by Andrew Beckett

    3 replies • 14061 views
  • Discussion

    VerilogA compiler

    Category: Custom IC Design

    By Sali

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    •

    updated over 11 years ago by Andrew Beckett

    11 replies • 21639 views
  • Discussion

    Import Stream (GDSII) from Encounter: Routing is dropped. (XSTRM-58)

    Category: Custom IC Design

    By bjbit

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    updated over 11 years ago by Ramil

    10 replies • 18508 views
  • Discussion

    ADE XL Error 5012 Netlisting issue with extracted parasitics

    Category: Custom IC Design

    By harleys

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    •

    updated over 11 years ago by harleys

    4 replies • 17786 views
  • Discussion

    cdb2oa migration (pcellEvalFailed)

    Category: Custom IC Design

    By Prasanna7

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    •

    updated over 11 years ago by theopaone

    1 replies • 14564 views
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