Custom IC Design

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Quantus QRC issue

Category: Custom IC Design

By HY20250821344

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updated 1 month ago by HY20250821344

2 replies • 1126 views
Discussion

Could not find netlist procedure:SpectreFNPairs instance

Category: Custom IC Design

By ranaya

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updated 2 months ago by Andrew Beckett

5 replies • 1012 views
Discussion

LUT implementation using VerilogA code In Cadence Virtuoso

Category: Custom IC Design

By ZulfiqarKiani

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started 2 months ago

0 replies • 864 views
Discussion

Sorting variables by name alphanumerically in Virtuoso ADE Assembler / maestro

Category: Custom IC Design

By Dominique8765

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updated 2 months ago by Andrew Beckett

1 replies • 636 views
Discussion

sweeping transistor number of fingers in a simulation

Category: Custom IC Design

By TommasoF

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updated 2 months ago by TommasoF

2 replies • 1116 views
Discussion

xrun: *F,SROOTE: Cannot find the Spectre installation

Category: Custom IC Design

By Leo 93

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updated 2 months ago by Andrew Beckett

3 replies • 658 views
Discussion

use DC sweep variable to set another variable

Category: Custom IC Design

By Darrell L

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updated 2 months ago by Darrell L

2 replies • 828 views
Discussion

automate cadence design to avoid time consuming steps for simulation using python subprocess module.

Category: Custom IC Design

By AP202507218251

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started 2 months ago

0 replies • 607 views
Discussion

ERROR (NVN-13010): Cell rupolym is not defined while running Pegasus LVS

Category: Custom IC Design

By yogeshjaiswalCAD

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updated 2 months ago by Andrew Beckett

3 replies • 924 views
Discussion

All pins on schematics unconnected to their attached wires when importing EDIF from Siemens,

Category: Custom IC Design

By DavidGogiber

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updated 2 months ago by Andrew Beckett

4 replies • 1209 views
Discussion

Cannot Copy Variable to Other Tests

Category: Custom IC Design

By MM202507017815

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updated 2 months ago by Andrew Beckett

1 replies • 709 views
Discussion

Cadence PEX Directory Creation - Unable to Create the Directory for Netlist

Category: Custom IC Design

By ranaya

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updated 2 months ago by ranaya

2 replies • 547 views
Discussion

Cadence Parasitic Extraction - Location / Directory Issue

Category: Custom IC Design

By ranaya

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updated 2 months ago by Andrew Beckett

1 replies • 377 views
Discussion

Automating Library Reference Change with Additional Parameters in New Library

Category: Custom IC Design

By AN202507174258

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started 2 months ago

0 replies • 674 views
Discussion

For a new machine, which RHEL?

Category: Custom IC Design

By kenc184

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updated 2 months ago by kenc184

3 replies • 1091 views

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