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Custom IC Design

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  • Discussion

    assura LVS unbound devices are IO cells

    Category: Custom IC Design

    By zczc99

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    updated over 11 years ago by Quek

    1 replies • 15653 views
  • Discussion

    cdb2oa error help!

    Category: Custom IC Design

    By blessingbox

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    updated over 11 years ago by Quek

    1 replies • 14466 views
  • Discussion

    Scale factor or unit problem in virtuoso schematic editor

    Category: Custom IC Design

    By simbamford

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    •

    updated over 11 years ago by Quek

    1 replies • 15291 views
  • Discussion

    Virtuoso XL editing capability is not enabled

    Category: Custom IC Design

    By ag2888

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    •

    updated over 11 years ago by Quek

    1 replies • 15129 views
  • Discussion

    Measuring device parameters with Assura

    Category: Custom IC Design

    By PietroUser

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    •

    updated over 11 years ago by Quek

    1 replies • 14025 views
  • Discussion

    Calculating the intersection point of 2 waveforms using the calculator

    Category: Custom IC Design

    By ag2888

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    •

    updated over 11 years ago by ag2888

    2 replies • 19848 views
  • Discussion

    auCdl view and loading CDF port order through CIW?

    Category: Custom IC Design

    By yayla

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    updated over 11 years ago by yayla

    1 replies • 16561 views
  • Discussion

    Stop Time in Transient Analysis

    Category: Custom IC Design

    By Hadi Hayati

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    updated over 11 years ago by Tawna

    6 replies • 22626 views
  • Discussion

    Can gzipped netlist be used in spectre?

    Category: Custom IC Design

    By sram8t

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    updated over 11 years ago by Tawna

    1 replies • 14189 views
  • Discussion

    Unable to get license feature

    Category: Custom IC Design

    By moo911940

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    •

    updated over 11 years ago by skillUser

    1 replies • 14790 views
  • Discussion

    Best way to make a serial stream (SPI) for VPWLF?

    Category: Custom IC Design

    By bpdegnan

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    updated over 11 years ago by Andrew Beckett

    2 replies • 14907 views
  • Discussion

    ADEGXL global optimisation runs only 9 jobs in parallel

    Category: Custom IC Design

    By vamshiky

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    •

    updated over 11 years ago by vamshiky

    2 replies • 14390 views
  • Discussion

    LDO pz analysis

    Category: Custom IC Design

    By potsticker

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    •

    started over 11 years ago

    0 replies • 14612 views
  • Discussion

    Unbound pin error from Assura LVS after P&R

    Category: Custom IC Design

    By bjbit

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    •

    updated over 11 years ago by alperro

    4 replies • 5887 views
  • Discussion

    Intrinsic capacitance Cbs

    Category: Custom IC Design

    By ronaldomponte

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    •

    updated over 11 years ago by ronaldomponte

    2 replies • 14794 views
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