Custom IC Design

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Discussion

Howto read port currents when having multi-terminal bus ports in VerilogA ?

Category: Custom IC Design

By Herge

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updated over 13 years ago by Herge

6 replies • 16780 views
Discussion

How to debug VerilogA compilation when code seems to check clean but simulation aborts when compiling ?

Category: Custom IC Design

By Herge

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updated over 13 years ago by Herge

3 replies • 15974 views
Discussion

montecarlo simulations beetween Wmin and Wmax for mos transistors

Category: Custom IC Design

By inessadm

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updated over 13 years ago by inessadm

2 replies • 14304 views
Discussion

Working with tabs in virtuoso schematic editor (opus 6.1.5 - ADE L)

Category: Custom IC Design

By Aldo2

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updated over 13 years ago by Aldo2

7 replies • 4775 views
Discussion

Virtuoso: "save a copy" from read-only cell in 6.1.4 but not in 6.1.5

Category: Custom IC Design

By StefanSL

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updated over 13 years ago by StefanSL

2 replies • 1383 views
Discussion

automatically spacing and aligning instances in Virtuoso schematic editor

Category: Custom IC Design

By MOSFET

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updated over 13 years ago by Andrew Beckett

1 replies • 18095 views
Discussion

Finding the maximum after a parametric analysis with more than one variable

Category: Custom IC Design

By Ueue

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updated over 13 years ago by Andrew Beckett

1 replies • 13605 views
Discussion

How to do a sp simulation using the netlist created by relxpert?

Category: Custom IC Design

By wyliechee

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updated over 13 years ago by Andrew Beckett

3 replies • 13878 views
Discussion

Cadence session crash.

Category: Custom IC Design

By maskdesigner

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updated over 13 years ago by Andrew Beckett

5 replies • 16771 views
Discussion

LVS with Calibre ("wrong floating n-well" error)

Category: Custom IC Design

By Ueue

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updated over 13 years ago by Andrew Beckett

1 replies • 4656 views
Discussion

cross probing with calibre

Category: Custom IC Design

By layout analog

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updated over 13 years ago by Andrew Beckett

1 replies • 13769 views
Discussion

Location of spectre for ADE L

Category: Custom IC Design

By jun1119

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updated over 13 years ago by Andrew Beckett

1 replies • 13623 views
Discussion

VerilogIn pin notation

Category: Custom IC Design

By TjaartOpperman

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updated over 13 years ago by Andrew Beckett

1 replies • 14711 views
Discussion

Measure across a component in cadence ic 6.1.3

Category: Custom IC Design

By jun1119

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updated over 13 years ago by Andrew Beckett

1 replies • 13833 views
Discussion

Assura TIE ivpcell substrateLib not found

Category: Custom IC Design

By Xiongliang

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updated over 13 years ago by Andrew Beckett

1 replies • 13745 views

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