Custom IC Design

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Discussion

Plotting a digital bus against an analog signal

Category: Custom IC Design

By ag2888

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started over 11 years ago

0 replies • 14300 views
Discussion

APS under ADE XL

Category: Custom IC Design

By Awny

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updated over 11 years ago by Andrew Beckett

1 replies • 14405 views
Discussion

Effect of mos fingering in schematic simulation

Category: Custom IC Design

By jdp721

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updated over 11 years ago by Andrew Beckett

1 replies • 14086 views
Discussion

stract error

Category: Custom IC Design

By pejman saleh

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updated over 11 years ago by Quek

1 replies • 13623 views
Discussion

Transistor multiplier is not getting changed

Category: Custom IC Design

By kapiljainwal

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started over 11 years ago

0 replies • 13583 views
Discussion

Assura LVS matches PVS LVS does not

Category: Custom IC Design

By MoMiner1870

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updated over 11 years ago by Andrew Beckett

1 replies • 14627 views
Discussion

Using MMSIM11.1 (64 bit) to simulate VerilogA modules

Category: Custom IC Design

By qnehal

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updated over 11 years ago by Andrew Beckett

5 replies • 15477 views
Discussion

Simulation License Queueing

Category: Custom IC Design

By XinjiePI

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updated over 11 years ago by Andrew Beckett

1 replies • 18446 views
Discussion

Export all plots in ADE XL

Category: Custom IC Design

By fanfanchan

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started over 11 years ago

0 replies • 13756 views
Discussion

print all mos opertion point to a file

Category: Custom IC Design

By xianweng

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started over 11 years ago

0 replies • 13385 views
Discussion

Problem in simulating a circuit with spectre

Category: Custom IC Design

By pdatta

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updated over 11 years ago by Andrew Beckett

5 replies • 18954 views
Discussion

How to not automatically open schematic view during opening layout XL?

Category: Custom IC Design

By Magistus

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updated over 11 years ago by Tom Volden

1 replies • 16201 views
Discussion

Layout problem . yellow warning - how to remove it?

Category: Custom IC Design

By Pyroblast

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updated over 11 years ago by theopaone

1 replies • 4299 views
Discussion

virtuoso transient parametric simulation : I functions of V (possibly with no ocean) [spectre]

Category: Custom IC Design

By samung

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updated over 11 years ago by samung

2 replies • 14764 views
Discussion

OSS-based netlister error with imported Verilog module

Category: Custom IC Design

By GabrielB

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updated over 11 years ago by GabrielB

1 replies • 16080 views

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